Beispiel #1
0
def test_ComplexBitBlast_8_to_1x8(setup_sim):
    model, sim = setup_bit_blast(setup_sim, 8, 8)
    model.in_.value = 0b11110000
    sim.eval_combinational()
    verify_bit_blast(model.out, 0b11110000)
    model.in_.value = 0b01010101
    sim.eval_combinational()
    verify_bit_blast(model.out, 0b01010101)
Beispiel #2
0
def test_SimpleBitBlast_16_to_16x1(setup_sim):
    model, sim = setup_bit_blast(setup_sim, 16)
    model.in_.v = 0b11110000
    sim.eval_combinational()
    verify_bit_blast(model.out, 0b11110000)
    model.in_.v = 0b1111000011001010
    sim.eval_combinational()
    verify_bit_blast(model.out, 0b1111000011001010)
def test_ComplexBitBlast_8_to_1x8( setup_sim ):
  model, sim = setup_bit_blast( setup_sim, 8, 8 )
  model.in_.value = 0b11110000
  sim.eval_combinational()
  verify_bit_blast( model.out, 0b11110000 )
  model.in_.value = 0b01010101
  sim.eval_combinational()
  verify_bit_blast( model.out, 0b01010101 )
def test_SimpleBitBlast_16_to_16x1( setup_sim ):
  model, sim = setup_bit_blast( setup_sim, 16 )
  model.in_.v = 0b11110000
  sim.eval_combinational()
  verify_bit_blast( model.out, 0b11110000 )
  model.in_.v = 0b1111000011001010
  sim.eval_combinational()
  verify_bit_blast( model.out, 0b1111000011001010 )
def register_bit_blast_tester( model, setup_sim ):
  model, sim = setup_sim( model )
  transl     = not hasattr( model, 'reg0' )
  sim.reset()
  model.in_.v = 0b11110000
  verify_bit_blast( model.out, 0b0 )
  if not transl: assert model.reg0.out.v  == 0b0
  sim.cycle()
  if not transl: assert model.reg0.out.v  == 0b11110000
  if not transl: assert model.split.in_.v == 0b11110000
  if not transl: verify_bit_blast( model.split.out, 0b11110000 )
  verify_bit_blast( model.out,       0b11110000 )
  model.in_.v = 0b1111000011001010
  if not transl: assert model.reg0.out.v  == 0b11110000
  if not transl: assert model.split.in_.v == 0b11110000
  if not transl: verify_bit_blast( model.split.out, 0b11110000 )
  verify_bit_blast( model.out,       0b11110000 )
  sim.cycle()
  if not transl: assert model.reg0.out.v  == 0b1111000011001010
  verify_bit_blast( model.out, 0b1111000011001010 )
def register_bit_blast_tester(model, setup_sim):
    model, sim = setup_sim(model)
    transl = not hasattr(model, 'reg0')
    sim.reset()
    model.in_.v = 0b11110000
    verify_bit_blast(model.out, 0b0)
    if not transl: assert model.reg0.out.v == 0b0
    sim.cycle()
    if not transl: assert model.reg0.out.v == 0b11110000
    if not transl: assert model.split.in_.v == 0b11110000
    if not transl: verify_bit_blast(model.split.out, 0b11110000)
    verify_bit_blast(model.out, 0b11110000)
    model.in_.v = 0b1111000011001010
    if not transl: assert model.reg0.out.v == 0b11110000
    if not transl: assert model.split.in_.v == 0b11110000
    if not transl: verify_bit_blast(model.split.out, 0b11110000)
    verify_bit_blast(model.out, 0b11110000)
    sim.cycle()
    if not transl: assert model.reg0.out.v == 0b1111000011001010
    verify_bit_blast(model.out, 0b1111000011001010)