def test_translation_temporary_scope(setup_sim):
class TestTranslationTemporaryScope(Model):
def __init__(s):
s.a = InPort(2)
s.b = InPort(2)
s.o = OutPort(1)
s.p = OutPort(1)
@s.combinational
def logic0():
temp = s.a > s.b
s.o.value = temp
@s.combinational
def logic1():
temp = s.b < s.a
s.p.value = temp
m, sim = setup_sim(TestTranslationTemporaryScope())
for i in range(10):
a, b = [randrange(0, 2**2) for _ in range(2)]
m.a.value, m.b.value = a, b
sim.cycle()
assert m.o == (1 if a > b else 0)
assert m.p == (1 if a > b else 0)
def test_translation_temporary_scope( setup_sim ):
class TestTranslationTemporaryScope( Model ):
def __init__( s ):
s.a = InPort ( 2 )
s.b = InPort ( 2 )
s.o = OutPort( 1 )
s.p = OutPort( 1 )
@s.combinational
def logic0():
temp = s.a > s.b
s.o.value = temp
@s.combinational
def logic1():
temp = s.b < s.a
s.p.value = temp
m, sim = setup_sim( TestTranslationTemporaryScope() )
for i in range(10):
a,b = [randrange(0,2**2) for _ in range(2)]
m.a.value, m.b.value = a, b
sim.cycle()
assert m.o == (1 if a > b else 0)
assert m.p == (1 if a > b else 0)
def test_translation_issue_88_d(setup_sim):
class TestTranslationIssue88_Dchild(Model):
def __init__(s):
s.in_ = InPort[1](4)
s.out = OutPort[1](4)
@s.combinational
def logic():
s.out[0].value = s.in_[0]
class TestTranslationIssue88_D(Model):
def __init__(s):
s.in_ = InPort[1](4)
s.out = OutPort[1](4)
s.isub = TestTranslationIssue88_Dchild[1]()
s.osub = TestTranslationIssue88_Dchild[1]()
s.connect(s.in_[0], s.isub[0].in_[0])
s.connect(s.out[0], s.osub[0].out[0])
@s.combinational
def logic():
s.osub[0].in_[0].value = s.isub[0].out[0]
m, sim = setup_sim(TestTranslationIssue88_D())
for i in range(10):
a = randrange(2**4)
m.in_[0].value = a
sim.cycle()
assert m.out[0] == a
def test_translation_bad_comparison( setup_sim, impl ):
class TestTranslationBadComparison( Model ):
def __init__( s, num ):
s.i = InPort ( 2 )
s.o = OutPort( 1 )
if num == 0:
@s.tick_rtl
def logic0():
s.o.next = 0 < s.i < 3
if num == 1:
@s.combinational
def logic0():
s.o.value = 0 < s.i < 3
if num == 2:
@s.tick_rtl
def logic0():
if 0 < s.i < 3: s.o.next = 1
else: s.o.next = 0
if num == 3:
@s.combinational
def logic0():
if 0 < s.i < 3: s.o.value = 1
else: s.o.value = 0
m, sim = setup_sim( TestTranslationBadComparison(impl) )
for i in range(10):
k = randrange(0,2**2)
m.i.value = k
sim.cycle()
assert m.o == (0 < k < 3)
def test_translation_issue_88_c( setup_sim ):
class TestTranslationIssue88_Cchild( Model ):
def __init__( s ):
s.in_ = InPort ( 4 )
s.out = OutPort( 4 )
@s.combinational
def logic():
s.out.value = s.in_.value
class TestTranslationIssue88_C( Model ):
def __init__( s ):
s.in_ = InPort [ 1 ]( 4 )
s.val = InPort [ 4 ]( 1 )
s.out = OutPort[ 1 ]( 4 )
s.isub = TestTranslationIssue88_Cchild[1]()
s.osub = TestTranslationIssue88_Cchild[1]()
s.connect( s.in_[0], s.isub[0].in_ )
s.connect( s.out[0], s.osub[0].out )
@s.combinational
def logic():
for i in range(4):
s.osub[0].in_[i].value = s.val[i] and s.isub[0].out[i]
m, sim = setup_sim( TestTranslationIssue88_C() )
for j in range(4):
m.val[j].value = 1
for i in range(10):
a = randrange(2**4)
m.in_[0].value = a
sim.cycle()
assert m.out[0] == a
def test_ListOfPortBundles( setup_sim ):
class ListOfPortBundlesStruct( Model ):
def __init__( s ):
s.in_ = [ InValRdyBundle ( 8 ) for x in range( 4 ) ]
s.out = [ OutValRdyBundle( 8 ) for x in range( 4 ) ]
for i in range( 4 ):
s.connect( s.in_[ i ], s.out[ i ] )
model = ListOfPortBundlesStruct()
model, sim = setup_sim( model )
sim.reset()
for i in range( 4 ):
# TODO add assert to prevent this
#model.in_[ i ].v = i
model.in_[ i ].msg.v = i
# if this is a verilog translation, need to perform a reset/cycle
# before this is applied
if is_translated( model ):
sim.eval_combinational()
for i in range( 4 ):
assert model.out[ i ].msg.v == i
def test_translation_keyword_args(setup_sim, num):
class TestTranslationKeywordArgs(Model):
def __init__(s, num):
s.a = InPort(8)
s.b = InPort(8)
s.out = OutPort(8)
if num == 0:
@s.posedge_clk
def logic():
s.out.next = Bits(8, 4, trunc=True)
print s.out.value
elif num == 1:
my_args = [8, 4]
@s.posedge_clk
def logic():
s.out.next = Bits(*my_args)
elif num == 2:
my_args = {'nbits': 8, 'value': 4}
@s.posedge_clk
def logic():
s.out.next = Bits(**my_args)
else:
raise Exception('Invalid Configuration!')
m, sim = setup_sim(TestTranslationKeywordArgs(num))
for i in range(10):
sim.cycle()
assert m.out == 4
def splitter_tester( setup_sim, model_type ): model = model_type( 16 ) model, sim = setup_sim( model ) # Note: no need to call cycle, no @combinational block unless it is a # Verilog translation. transl = is_translated( model ) model.in_.v = 8 # call eval if this is a Verilog translated model if transl: sim.eval_combinational() assert model.out0 == 8 assert model.out0.v == 8 assert model.out1 == 8 assert model.out1.v == 8 model.in_.v = 9 model.in_.v = 10 # call eval if this is a Verilog translated model if transl: sim.eval_combinational() assert model.out0 == 10 assert model.out1 == 10
def test_translation_bad_comparison( setup_sim, impl ):
class TestTranslationBadComparison( Model ):
def __init__( s, num ):
s.i = InPort ( 2 )
s.o = OutPort( 1 )
if num == 0:
@s.tick_rtl
def logic0():
s.o.next = 0 < s.i < 3
if num == 1:
@s.combinational
def logic0():
s.o.value = 0 < s.i < 3
if num == 2:
@s.tick_rtl
def logic0():
if 0 < s.i < 3: s.o.next = 1
else: s.o.next = 0
if num == 3:
@s.combinational
def logic0():
if 0 < s.i < 3: s.o.value = 1
else: s.o.value = 0
m, sim = setup_sim( TestTranslationBadComparison(impl) )
for i in range(10):
k = randrange(0,2**2)
m.i.value = k
sim.cycle()
assert m.o == (0 < k < 3)
def test_WriteThenReadWire(setup_sim):
class WriteThenReadWire(Model):
def __init__(s, nbits):
s.in_ = InPort(nbits)
s.out = OutPort(nbits)
s.temp = Wire(nbits)
@s.combinational
def comb_logic():
s.temp.v = s.in_
s.out.v = s.temp
# Temporary workaround
# @s.combinational
# def comb_logic():
# s.temp.v = s.in_
# @s.combinational
# def comb_logic():
# s.out.v = s.temp
model = WriteThenReadWire(16)
model, sim = setup_sim(model)
for i in range(10):
model.in_.v = i
# assert False # Prevent infinite loop!
sim.eval_combinational()
assert model.out == i
def test_WriteThenReadWire(setup_sim):
class WriteThenReadWire(Model):
def __init__(s, nbits):
s.in_ = InPort(nbits)
s.out = OutPort(nbits)
s.temp = Wire(nbits)
@s.combinational
def comb_logic():
s.temp.v = s.in_
s.out.v = s.temp
# Temporary workaround
#@s.combinational
#def comb_logic():
# s.temp.v = s.in_
#@s.combinational
#def comb_logic():
# s.out.v = s.temp
model = WriteThenReadWire(16)
model, sim = setup_sim(model)
for i in range(10):
model.in_.v = i
#assert False # Prevent infinite loop!
sim.eval_combinational()
assert model.out == i
def splitter_tester(setup_sim, model_type):
model = model_type(16)
model, sim = setup_sim(model)
# Note: no need to call cycle, no @combinational block unless it is a
# Verilog translation.
transl = is_translated(model)
model.in_.v = 8
# call eval if this is a Verilog translated model
if transl: sim.eval_combinational()
assert model.out0 == 8
assert model.out0.v == 8
assert model.out1 == 8
assert model.out1.v == 8
model.in_.v = 9
model.in_.v = 10
# call eval if this is a Verilog translated model
if transl: sim.eval_combinational()
assert model.out0 == 10
assert model.out1 == 10
def setup_bit_merge(setup_sim, nbits, groups=None):
if not groups:
model = SimpleBitMergeStruct(nbits)
else:
model = ComplexBitMergeStruct(nbits, groups)
model, sim = setup_sim(model)
return model, sim
def test_translation_issue_88_d( setup_sim ):
class TestTranslationIssue88_Dchild( Model ):
def __init__( s ):
s.in_ = InPort [1]( 4 )
s.out = OutPort[1]( 4 )
@s.combinational
def logic():
s.out[0].value = s.in_[0]
class TestTranslationIssue88_D( Model ):
def __init__( s ):
s.in_ = InPort [ 1 ]( 4 )
s.out = OutPort[ 1 ]( 4 )
s.isub = TestTranslationIssue88_Dchild[1]()
s.osub = TestTranslationIssue88_Dchild[1]()
s.connect( s.in_[0], s.isub[0].in_[0] )
s.connect( s.out[0], s.osub[0].out[0] )
@s.combinational
def logic():
s.osub[0].in_[0].value = s.isub[0].out[0]
m, sim = setup_sim( TestTranslationIssue88_D() )
for i in range(10):
a = randrange(2**4)
m.in_[0].value = a
sim.cycle()
assert m.out[0] == a
def test_translation_keyword_args( setup_sim, num ):
class TestTranslationKeywordArgs( Model ):
def __init__( s, num ):
s.a = InPort ( 8 )
s.b = InPort ( 8 )
s.out = OutPort( 8 )
if num == 0:
@s.posedge_clk
def logic():
s.out.next = Bits(8, 4, trunc=True)
print s.out.value
elif num == 1:
my_args = [8,4]
@s.posedge_clk
def logic():
s.out.next = Bits( *my_args )
elif num == 2:
my_args = { 'nbits':8, 'value':4 }
@s.posedge_clk
def logic():
s.out.next = Bits( **my_args )
else:
raise Exception('Invalid Configuration!')
m, sim = setup_sim( TestTranslationKeywordArgs(num) )
for i in range(10):
sim.cycle()
assert m.out == 4
def test_translation_iter_unsupported_step(setup_sim, num):
class TestTranslationIterUnsupportedStep(Model):
def __init__(s, num):
s.in_ = InPort(8)
s.out = OutPort(8)
if num == 0:
@s.combinational
def logic0():
for i in range(0, 8, 0):
s.out[i].value = s.in_[i]
elif num == 1:
@s.combinational
def logic0():
for i in range(0, 8, 0 + 1):
s.out[i].value = s.in_[i]
elif num == 2:
@s.combinational
def logic0():
for i in range(7, -1, 0 - 1):
s.out[i].value = s.in_[i]
else:
raise Exception('Invalid Configuration!')
n = 4
m, sim = setup_sim(TestTranslationIterUnsupportedStep(num))
for i in range(10):
k = Bits(n, randrange(0, 2**n))
m.in_.value = k
sim.cycle()
assert m.out == k
def test_translation_iter_unsupported_step( setup_sim, num ):
class TestTranslationIterUnsupportedStep( Model ):
def __init__( s, num ):
s.in_ = InPort ( 8 )
s.out = OutPort( 8 )
if num == 0:
@s.combinational
def logic0():
for i in range( 0, 8, 0 ):
s.out[i].value = s.in_[i]
elif num == 1:
@s.combinational
def logic0():
for i in range( 0, 8, 0+1 ):
s.out[i].value = s.in_[i]
elif num == 2:
@s.combinational
def logic0():
for i in range( 7,-1, 0-1 ):
s.out[i].value = s.in_[i]
else:
raise Exception('Invalid Configuration!')
n = 4
m, sim = setup_sim( TestTranslationIterUnsupportedStep(num) )
for i in range(10):
k = Bits(n,randrange(0,2**n))
m.in_.value = k
sim.cycle()
assert m.out == k
def setup_bit_merge( setup_sim, nbits, groups=None ):
if not groups:
model = SimpleBitMergeStruct( nbits )
else:
model = ComplexBitMergeStruct( nbits, groups )
model, sim = setup_sim( model )
return model, sim
def test_translation_issue_88_c(setup_sim):
class TestTranslationIssue88_Cchild(Model):
def __init__(s):
s.in_ = InPort(4)
s.out = OutPort(4)
@s.combinational
def logic():
s.out.value = s.in_.value
class TestTranslationIssue88_C(Model):
def __init__(s):
s.in_ = InPort[1](4)
s.val = InPort[4](1)
s.out = OutPort[1](4)
s.isub = TestTranslationIssue88_Cchild[1]()
s.osub = TestTranslationIssue88_Cchild[1]()
s.connect(s.in_[0], s.isub[0].in_)
s.connect(s.out[0], s.osub[0].out)
@s.combinational
def logic():
for i in range(4):
s.osub[0].in_[i].value = s.val[i] and s.isub[0].out[i]
m, sim = setup_sim(TestTranslationIssue88_C())
for j in range(4):
m.val[j].value = 1
for i in range(10):
a = randrange(2**4)
m.in_[0].value = a
sim.cycle()
assert m.out[0] == a
def test_ConnectPairs( setup_sim ):
class ConnectPairs( Model ):
def __init__( s, config ):
s.a = InPort [ 4 ]( 8 )
s.b = OutPort[ 4 ]( 8 )
if config == 'good':
s.connect_pairs(
s.a[0], s.b[0],
s.a[1], s.b[1],
s.a[2], s.b[2],
s.a[3], s.b[3],
)
elif config == 'bad':
s.connect_pairs(
s.a[0], s.b[0],
s.a[1], s.b[1],
s.a[2], s.b[2],
s.a[3],
)
with pytest.raises( pymtl.model.ConnectionEdge.PyMTLConnectError ):
model = ConnectPairs('bad')
model = ConnectPairs('good')
model, sim = setup_sim( model )
sim.reset()
for i in range( 5 ):
for j in range( 4 ): model.a[j].value = i+j
sim.cycle()
for j in range( 4 ): model.b[j] == i+j
def test_WriteThenReadCombSubmod( setup_sim ):
model = WriteThenReadCombSubmod( 16 )
model, sim = setup_sim( model )
for i in range( 10 ):
model.in_.v = i
#assert False # Prevent infinite loop!
sim.cycle()
assert model.out == i
def test_WireToWire2( setup_sim ):
with pytest.raises( pymtl.model.ConnectionEdge.PyMTLConnectError ):
model = WireToWire( 8, test='raise_bad' )
model = WireToWire( 8, test='bad' )
model, sim = setup_sim( model )
for i in range( 10 ):
model.in_.value = i; sim.cycle(); assert model.out == i
def test_WriteThenReadCombSubmod(setup_sim):
model = WriteThenReadCombSubmod(16)
model, sim = setup_sim(model)
for i in range(10):
model.in_.v = i
#assert False # Prevent infinite loop!
sim.cycle()
assert model.out == i
def test_BitStructLocal( setup_sim, src, dest ):
class BitStructLocal( BitStructDefinition ):
def __init__( s, src_nbits, dest_nbits ):
s.src = BitField( src_nbits )
s.dest = BitField( dest_nbits )
model = BitStructConnect( BitStructLocal( src, dest ) )
model, sim = setup_sim( model )
bitstruct_verifier( model, sim, src, dest )
def test_BitStructLocal(setup_sim, src, dest):
class BitStructLocal(BitStructDefinition):
def __init__(s, src_nbits, dest_nbits):
s.src = BitField(src_nbits)
s.dest = BitField(dest_nbits)
model = BitStructConnect(BitStructLocal(src, dest))
model, sim = setup_sim(model)
bitstruct_verifier(model, sim, src, dest)
def test_WireToWire2(setup_sim):
with pytest.raises(pymtl.model.ConnectionEdge.PyMTLConnectError):
model = WireToWire(8, test='raise_bad')
model = WireToWire(8, test='bad')
model, sim = setup_sim(model)
for i in range(10):
model.in_.value = i
sim.cycle()
assert model.out == i
def test_NStageComb(setup_sim):
model = NStageComb(16, 3)
model, sim = setup_sim(model)
# fill up the pipeline
for i in range(10):
model.in_.v = i
expected = (i - 1) if (i - 1) >= 0 else 0
assert model.out == expected
#assert False # Prevent infinite loop!
sim.cycle()
def test_NStageComb(setup_sim):
model = NStageComb(16, 3)
model, sim = setup_sim(model)
# fill up the pipeline
for i in range(10):
model.in_.v = i
expected = (i - 1) if (i - 1) >= 0 else 0
assert model.out == expected
# assert False # Prevent infinite loop!
sim.cycle()
def test_WireToWire1(setup_sim):
with pytest.raises(pymtl.model.ConnectionEdge.PyMTLConnectError):
model = WireToWire(8, test="raise_good")
model = WireToWire(8, test="good")
model, sim = setup_sim(model)
for i in range(10):
model.in_.value = i
sim.cycle()
assert model.out == i
def test_translation_func_not_int(setup_sim, num):
class TestTranslationFuncNotInt(Model):
def __init__(s, num):
s.in_ = InPort(4)
s.out = OutPort(8)
if num == 0:
@s.combinational
def logic0():
s.out.value = sext(s.in_, 8.1)
elif num == 1:
@s.combinational
def logic0():
s.out.value = zext(s.in_, 8.1)
elif num == 2:
@s.combinational
def logic0():
s.out.value = Bits(8.1, s.in_)
elif num == 3:
@s.combinational
def logic0():
s.out.value = sext(s.in_, 4 + 4)
elif num == 4:
@s.combinational
def logic0():
s.out.value = zext(s.in_, 4 + 4)
elif num == 5:
@s.combinational
def logic0():
s.out.value = Bits(4 + 4, s.in_)
else:
raise Exception('Invalid Configuration!')
m, sim = setup_sim(TestTranslationFuncNotInt(num))
for i in range(10):
k = Bits(4, randrange(0, 2**4))
m.in_.value = k
sim.cycle()
if num == 0: assert m.out == sext(k, 8)
elif num == 1: assert m.out == k
elif num == 2: assert m.out == k
def test_translation_bits_constr(setup_sim, num):
class TestTranslationBitsConstr(Model):
def __init__(s, num):
s.a = InPort(8)
s.out = OutPort(16)
if num == 0:
@s.posedge_clk
def logic():
s.out.next = Bits(16)
elif num == 1:
@s.posedge_clk
def logic():
s.out.next = Bits(16, 1)
elif num == 2:
s.tmp = num
@s.posedge_clk
def logic():
s.out.next = Bits(16, s.tmp)
elif num == 3:
tmp = num
@s.posedge_clk
def logic():
s.out.next = Bits(16, tmp)
elif num == 4:
s.tmp = 16
@s.posedge_clk
def logic():
s.out.next = Bits(s.tmp, 4)
elif num == 5:
tmp = 16
@s.posedge_clk
def logic():
s.out.next = Bits(tmp, 5)
else:
raise Exception('Invalid Configuration!')
m, sim = setup_sim(TestTranslationBitsConstr(num))
for i in range(10):
sim.cycle()
assert m.out == num
def test_ConstantSlice( setup_sim ):
model = ConstantSlice()
model, sim = setup_sim( model )
# if this is a verilog translation, need to perform a reset/cycle
# before this is applied
if is_translated( model ):
sim.eval_combinational()
assert model.out.v[ 0:16] == 4
assert model.out.v[16:32] == 8
sim.cycle()
assert model.out.v[ 0:16] == 4
assert model.out.v[16:32] == 8
def pipeline_tester(setup_sim, model, nstages):
model, sim = setup_sim(model)
# fill up the pipeline
for i in range(10):
model.in_.v = i
expected = (i - nstages + 1) if (i - nstages + 1) >= 0 else 0
assert model.out == expected
sim.cycle()
# drain the pipeline
for i in range(10 - nstages + 1, 10):
assert model.out == i
sim.cycle()
assert model.out == 9
def test_ConstantPort( setup_sim ):
model = ConstantPort()
model, sim = setup_sim( model )
# if this is a verilog translation, need to perform a reset/cycle
# before this is applied
if is_translated( model ):
sim.eval_combinational()
assert model.out == 4
# TODO: catch writing to a constant?
sim.cycle()
assert model.out == 4
def splitslice_tester( model_type, setup_sim ): model = model_type() model, sim = setup_sim( model ) sim.cycle() model.in_.v = 0b1001 assert model.out0 == 0b00 assert model.out1 == 0b00 sim.cycle() assert model.out0 == 0b01 assert model.out1 == 0b10 model.in_.v = 0b1111 sim.cycle() assert model.out0 == 0b11 assert model.out1 == 0b11
def test_ConstantPort(setup_sim):
model = ConstantPort()
model, sim = setup_sim(model)
# if this is a verilog translation, need to perform a reset/cycle
# before this is applied
if is_translated(model):
sim.eval_combinational()
assert model.out == 4
# TODO: catch writing to a constant?
sim.cycle()
assert model.out == 4
def pipeline_tester(setup_sim, model, nstages):
model, sim = setup_sim(model)
# fill up the pipeline
for i in range(10):
model.in_.v = i
expected = (i - nstages + 1) if (i - nstages + 1) >= 0 else 0
assert model.out == expected
sim.cycle()
# drain the pipeline
for i in range(10 - nstages + 1, 10):
assert model.out == i
sim.cycle()
assert model.out == 9
def test_ConstantSlice(setup_sim):
model = ConstantSlice()
model, sim = setup_sim(model)
# if this is a verilog translation, need to perform a reset/cycle
# before this is applied
if is_translated(model):
sim.eval_combinational()
assert model.out.v[0:16] == 4
assert model.out.v[16:32] == 8
sim.cycle()
assert model.out.v[0:16] == 4
assert model.out.v[16:32] == 8
def splitslice_tester(model_type, setup_sim):
model = model_type()
model, sim = setup_sim(model)
sim.cycle()
model.in_.v = 0b1001
assert model.out0 == 0b00
assert model.out1 == 0b00
sim.cycle()
assert model.out0 == 0b01
assert model.out1 == 0b10
model.in_.v = 0b1111
sim.cycle()
assert model.out0 == 0b11
assert model.out1 == 0b11
def test_translation_bad_decorator( setup_sim ):
class TestTranslationBadDecorator( Model ):
def __init__( s ):
s.i = InPort ( 2 )
s.o = OutPort( 2 )
@s.tick_cl
def logic0():
s.o.next = s.i
m, sim = setup_sim( TestTranslationBadDecorator() )
for i in range(10):
k = randrange(0,2**2)
m.i.value = k
sim.cycle()
assert m.o == k
def register_tester( model_type, setup_sim ): model = model_type( 16 ) model, sim = setup_sim( model ) model.in_.v = 8 assert model.out == 0 sim.cycle() assert model.out == 8 model.in_.v = 9 assert model.out == 8 model.in_.v = 10 sim.cycle() assert model.out == 10 model.in_.v = 2 sim.cycle() assert model.out == 2
def register_tester(model_type, setup_sim):
model = model_type(16)
model, sim = setup_sim(model)
model.in_.v = 8
assert model.out == 0
sim.cycle()
assert model.out == 8
model.in_.v = 9
assert model.out == 8
model.in_.v = 10
sim.cycle()
assert model.out == 10
model.in_.v = 2
sim.cycle()
assert model.out == 2
def test_ConstantModule( setup_sim ): model = ConstantModule() model, sim = setup_sim( model ) sim.reset() model.in_.v = 0b1111 sim.eval_combinational() assert model.out == 0b111100 sim.cycle() model.in_.v = 0b0101 sim.cycle() assert model.out == 0b010100 model.in_.v = 0b110110 sim.cycle() assert model.out == 0b11011000 sim.cycle()
def test_translation_slices03( setup_sim ):
class TestTranslationSlices03( Model ):
def __init__( s ):
s.i = InPort ( 16 )
s.o = OutPort( 6 )
off = 8
@s.combinational
def logic():
s.o.value = s.i[0:off-2]
m, sim = setup_sim( TestTranslationSlices03() )
for i in range(10):
val = Bits(16, randrange(0,2**16) )
m.i.value = val
sim.cycle()
assert m.o == val[:8-2]
def test_translation_bad_decorator( setup_sim ):
class TestTranslationBadDecorator( Model ):
def __init__( s ):
s.i = InPort ( 2 )
s.o = OutPort( 2 )
@s.tick_cl
def logic0():
s.o.next = s.i
m, sim = setup_sim( TestTranslationBadDecorator() )
for i in range(10):
k = randrange(0,2**2)
m.i.value = k
sim.cycle()
assert m.o == k
def test_translation_slices03( setup_sim ):
class TestTranslationSlices03( Model ):
def __init__( s ):
s.i = InPort ( 16 )
s.o = OutPort( 6 )
off = 8
@s.combinational
def logic():
s.o.value = s.i[0:off-2]
m, sim = setup_sim( TestTranslationSlices03() )
for i in range(10):
val = Bits(16, randrange(0,2**16) )
m.i.value = val
sim.cycle()
assert m.o == val[:8-2]
def test_ConstantModule(setup_sim):
model = ConstantModule()
model, sim = setup_sim(model)
sim.reset()
model.in_.v = 0b1111
sim.eval_combinational()
assert model.out == 0b111100
sim.cycle()
model.in_.v = 0b0101
sim.cycle()
assert model.out == 0b010100
model.in_.v = 0b110110
sim.cycle()
assert model.out == 0b11011000
sim.cycle()
def test_translation_bits_constr( setup_sim, num ):
class TestTranslationBitsConstr( Model ):
def __init__( s, num ):
s.a = InPort ( 8 )
s.out = OutPort( 16 )
if num == 0:
@s.posedge_clk
def logic():
s.out.next = Bits(16)
elif num == 1:
@s.posedge_clk
def logic():
s.out.next = Bits(16, 1)
elif num == 2:
s.tmp = num
@s.posedge_clk
def logic():
s.out.next = Bits(16, s.tmp)
elif num == 3:
tmp = num
@s.posedge_clk
def logic():
s.out.next = Bits(16, tmp)
elif num == 4:
s.tmp = 16
@s.posedge_clk
def logic():
s.out.next = Bits(s.tmp, 4)
elif num == 5:
tmp = 16
@s.posedge_clk
def logic():
s.out.next = Bits(tmp, 5)
else:
raise Exception('Invalid Configuration!')
m, sim = setup_sim( TestTranslationBitsConstr(num) )
for i in range(10):
sim.cycle()
assert m.out == num
def test_translation_func_not_int( setup_sim, num ):
class TestTranslationFuncNotInt( Model ):
def __init__( s, num ):
s.in_ = InPort ( 4 )
s.out = OutPort( 8 )
if num == 0:
@s.combinational
def logic0():
s.out.value = sext( s.in_, 8.1 )
elif num == 1:
@s.combinational
def logic0():
s.out.value = zext( s.in_, 8.1 )
elif num == 2:
@s.combinational
def logic0():
s.out.value = Bits( 8.1, s.in_ )
elif num == 3:
@s.combinational
def logic0():
s.out.value = sext( s.in_, 4+4 )
elif num == 4:
@s.combinational
def logic0():
s.out.value = zext( s.in_, 4+4 )
elif num == 5:
@s.combinational
def logic0():
s.out.value = Bits( 4+4, s.in_ )
else:
raise Exception('Invalid Configuration!')
m, sim = setup_sim( TestTranslationFuncNotInt(num) )
for i in range(10):
k = Bits(4,randrange(0,2**4))
m.in_.value = k
sim.cycle()
if num == 0: assert m.out == sext( k, 8 )
elif num == 1: assert m.out == k
elif num == 2: assert m.out == k
def test_SliceWriteCheck( setup_sim ):
model = SliceWriteCheck( 16 )
model, sim = setup_sim( model )
assert model.out == 0
# Test regular write
model.in_.n = 8
sim.cycle()
assert model.out == 0b1000
# Slice then .n, should pass
model.in_[0].n = 1
sim.cycle()
assert model.out == 0b1001
model.in_[4:8].n = 0b1001
sim.cycle()
assert model.out == 0b10011001
# Test regular write
model.in_.n = 8
sim.cycle()
assert model.out == 0b1000
# Only slice, should fail
model.in_[0] = 1
sim.cycle()
with pytest.raises( AssertionError ):
assert model.out == 0b1001
model.in_[4:8] = 0b1001
sim.cycle()
with pytest.raises( AssertionError ):
assert model.out == 0b10011001
# Test regular write
model.in_.n = 8
sim.cycle()
assert model.out == 0b1000
# .n then slice, should fail
model.in_.n[0] = 1
sim.cycle()
with pytest.raises( AssertionError ):
assert model.out == 0b1001
model.in_.n[4:8] = 0b1001
sim.cycle()
with pytest.raises( AssertionError ):
assert model.out == 0b10011001
def test_SliceWriteCheck(setup_sim):
model = SliceWriteCheck(16)
model, sim = setup_sim(model)
assert model.out == 0
# Test regular write
model.in_.n = 8
sim.cycle()
assert model.out == 0b1000
# Slice then .n, should pass
model.in_[0].n = 1
sim.cycle()
assert model.out == 0b1001
model.in_[4:8].n = 0b1001
sim.cycle()
assert model.out == 0b10011001
# Test regular write
model.in_.n = 8
sim.cycle()
assert model.out == 0b1000
# Only slice, should fail
model.in_[0] = 1
sim.cycle()
with pytest.raises(AssertionError):
assert model.out == 0b1001
model.in_[4:8] = 0b1001
sim.cycle()
with pytest.raises(AssertionError):
assert model.out == 0b10011001
# Test regular write
model.in_.n = 8
sim.cycle()
assert model.out == 0b1000
# .n then slice, should fail
model.in_.n[0] = 1
sim.cycle()
with pytest.raises(AssertionError):
assert model.out == 0b1001
model.in_.n[4:8] = 0b1001
sim.cycle()
with pytest.raises(AssertionError):
assert model.out == 0b10011001
def test_translation_loopvar_port_name_conflict( setup_sim ):
class TestTranslationLoopvarPortNameConflict( Model ):
def __init__( s ):
s.i = InPort ( 2 )
s.o = OutPort( 2 )
@s.tick_rtl
def logic0():
for i in range( 2 ):
s.o[i].next = s.i[i]
m, sim = setup_sim( TestTranslationLoopvarPortNameConflict() )
for i in range(10):
k = randrange(0,2**2)
m.i.value = k
sim.cycle()
assert m.o == k
def test_translation_bit_iterator( setup_sim ):
class TestTranslationBitIterator( Model ):
def __init__( s ):
s.i = InPort ( 2 )
s.o = OutPort( 2 )
@s.tick_rtl
def logic0():
for x in range( 2 ):
s.o[x].next = s.i[x]
m, sim = setup_sim( TestTranslationBitIterator() )
for i in range(10):
k = randrange(0,2**2)
m.i.value = k
sim.cycle()
assert m.o == k
def test_translation_loopvar_port_name_conflict( setup_sim ):
class TestTranslationLoopvarPortNameConflict( Model ):
def __init__( s ):
s.i = InPort ( 2 )
s.o = OutPort( 2 )
@s.tick_rtl
def logic0():
for i in range( 2 ):
s.o[i].next = s.i[i]
m, sim = setup_sim( TestTranslationLoopvarPortNameConflict() )
for i in range(10):
k = randrange(0,2**2)
m.i.value = k
sim.cycle()
assert m.o == k
def test_translation_bit_iterator( setup_sim ):
class TestTranslationBitIterator( Model ):
def __init__( s ):
s.i = InPort ( 2 )
s.o = OutPort( 2 )
@s.tick_rtl
def logic0():
for x in range( 2 ):
s.o[x].next = s.i[x]
m, sim = setup_sim( TestTranslationBitIterator() )
for i in range(10):
k = randrange(0,2**2)
m.i.value = k
sim.cycle()
assert m.o == k
def test_translation_issue_88(setup_sim, num):
class TestTranslationIssue88(Model):
def __init__(s, num, nports=2, size=4):
addr_sz = clog2(size)
s.wr_addr = InPort[nports](addr_sz)
s.wr_data = InPort[nports](8)
s.rd_data = OutPort[size](8)
s.regs = Wire[size](8)
if num == 0:
@s.posedge_clk
def write_logic():
for i in range(nports):
s.regs[s.wr_addr[i]].next = s.wr_data[i]
elif num == 1:
@s.posedge_clk
def write_logic():
for i in range(nports):
j = s.wr_addr[i]
s.regs[j].next = s.wr_data[i]
else:
raise Exception('Invalid Configuration!')
@s.combinational
def read_logic():
for i in range(size):
s.rd_data[i].value = s.regs[i]
m, sim = setup_sim(TestTranslationIssue88(num))
for i in range(10):
# ensure no addr conflict in write ports
a_addr, b_addr = randrange(0, 2), randrange(2, 4)
a_data, b_data = [randrange(0, 2**8) for _ in range(2)]
m.wr_addr[0].value = a_addr
m.wr_addr[1].value = b_addr
m.wr_data[0].value = a_data
m.wr_data[1].value = b_data
sim.cycle()
assert m.rd_data[a_addr] == a_data
assert m.rd_data[b_addr] == b_data
def test_translation_for_loop_enumerate_comb( setup_sim ):
class TestTranslationLoopEnumerateComb( Model ):
def __init__( s ):
s.i = InPort [4]( 2 )
s.o = OutPort[4]( 2 )
@s.combinational
def logic0():
for x, inport in enumerate( s.i ):
s.o[x].value = inport
m, sim = setup_sim( TestTranslationLoopEnumerateComb() )
for i in range(10):
js = [randrange(0,2**2) for _ in range( 4 )]
for k in range(4): m.i[k].value = js[k]
sim.cycle()
for k in range(4): assert m.o[k] == js[k]
def test_translation_true_false(setup_sim):
class TestTranslationTrueFalse(Model):
def __init__(s):
s.i = InPort(2)
s.o = OutPort(1)
@s.combinational
def logic():
if s.i > 2: s.o.value = True
else: s.o.value = False
m, sim = setup_sim(TestTranslationTrueFalse())
for i in range(10):
val = randrange(0, 2**2)
m.i.value = val
sim.cycle()
assert m.o == (val > 2)
def test_translation_for_loop_enumerate_comb( setup_sim ):
class TestTranslationLoopEnumerateComb( Model ):
def __init__( s ):
s.i = InPort [4]( 2 )
s.o = OutPort[4]( 2 )
@s.combinational
def logic0():
for x, inport in enumerate( s.i ):
s.o[x].value = inport
m, sim = setup_sim( TestTranslationLoopEnumerateComb() )
for i in range(10):
js = [randrange(0,2**2) for _ in range( 4 )]
for k in range(4): m.i[k].value = js[k]
sim.cycle()
for k in range(4): assert m.o[k] == js[k]
def test_translation_multiple_lhs_targets(setup_sim):
class TestTranslationMultipleLHS_Targets(Model):
def __init__(s):
s.i0 = InPort(2)
s.o0 = OutPort(2)
s.o1 = OutPort(2)
@s.combinational
def logic0():
s.o0.value = s.o1.value = s.i0
m, sim = setup_sim(TestTranslationMultipleLHS_Targets())
for i in range(10):
a = randrange(0, 2**2)
m.i0.value = a
sim.cycle()
assert m.o0 == a
assert m.o1 == a
