def ffd(f1, f2):
siglist = list()
for r in range(2, 4):
for c in range(2, 4):
for alu_inst in range(0, 8):
siglist.append(hier)
vcd1 = parse_vcd(f1, siglist=siglist)
vcd2 = parse_vcd(f2, siglist=siglist)
diff = deepdiff.DeepDiff(vcd1, vcd2)
print(json.dumps(diff, indent=4))
return
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
forks = []
def map(component, net, apply, delay=0):
forks.append(cocotb.fork(stim(wave, component, net, apply, delay)))
wave = parse_vcd(
"../../../../../../../simWorkspace/SdramXdrCtrlPlusRtlPhy/test.vcd")
top = "TOP"
yield Timer(0)
phaseCount = getLastValue(wave, top, "phaseCount")
clockPeriod = getClockPeriod(wave, top, "clk")
cocotb.fork(genClock(dut.Clk, None, clockPeriod // phaseCount))
list(map(top, "ADDR", lambda v: dut.Addr <= v))
list(map(top, "BA", lambda v: dut.Ba <= v))
list(map(top, "CASn", lambda v: dut.Cas_n <= v))
list(map(top, "CKE", lambda v: dut.Cke <= v))
list(map(top, "CSn", lambda v: dut.Cs_n <= v))
list(map(top, "RASn", lambda v: dut.Ras_n <= v))
list(map(top, "WEn", lambda v: dut.We_n <= v))
for fork in forks:
yield fork
def vcd_to_dic(vcd_file, filter=None):
vcd = parse_vcd(vcd_file)
signals = {}
for k in vcd.keys():
net = vcd[k]['nets'][0]
signal = net['hier'] + '.' + net['name']
if filter:
signal = re.sub('^' + filter + '.*?\.', '', signal)
signals[signal] = {}
signals[signal]['size'] = net['size']
signals[signal]['tv'] = to_fixed_size(vcd[k]['tv'],
int(net['size'], 10))
return signals
def extract_tracing_information(self, vcd_file, testbench_module_name):
# Grab the required signal trace from the VCD file
parsed = [
v['tv'] for _, v in
parse_vcd(str(vcd_file),
siglist=["{0}.tracer.trace_data_o[31:0]".format(testbench_module_name)],
opt_timescale="ns").items()
][0]
# Reformat the data so that it's an object containing each data
# item rather than one large bit string.
processed_data = [(time, TraceElement(bitstring, [["pass_through"]],
self.trace_element_mapping))
for (time, bitstring) in parsed[1:]]
return processed_data
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
forks = []
def map(component, net, apply, delay=0):
forks.append(cocotb.fork(stim(wave, component, net, apply, delay)))
wave = parse_vcd(
"../../../../../../../simWorkspace/SdramXdrCtrlPlusRtlPhy/test.vcd")
phy = "TOP.SdramXdrCtrlPlusRtlPhy"
top = "TOP"
yield Timer(0)
phaseCount = getLastValue(wave, top, "phaseCount")
dataRate = 2
phaseDelay = 0
clockPeriod = getClockPeriod(wave, top, "clk")
cocotb.fork(genClock(dut.ck, dut.ck_n, clockPeriod // phaseCount))
list(map(top, "ADDR", lambda v: dut.addr <= v))
list(map(top, "BA", lambda v: dut.ba <= v))
list(map(top, "CASn", lambda v: dut.cas_n <= v))
list(map(top, "CKE", lambda v: dut.cke <= v))
list(map(top, "CSn", lambda v: dut.cs_n <= v))
list(map(top, "RASn", lambda v: dut.ras_n <= v))
list(map(top, "WEn", lambda v: dut.we_n <= v))
list(map(top, "RESETn", lambda v: dut.rst_n <= v))
list(map(top, "ODT", lambda v: dut.odt <= v))
cocotb.fork(
stimPulse(
wave, top, "writeEnable", lambda v: cocotb.fork(
genDqs(
dut.dqs, dut.dqs_n, 1 + v / clockPeriod * phaseCount *
dataRate // 2, clockPeriod // (phaseCount * dataRate) *
(phaseCount * dataRate - 1), clockPeriod // phaseCount))))
for fork in forks:
yield fork
#!/usr/bin/env python3
from Verilog_VCD.Verilog_VCD import parse_vcd
from os import system
from sys import argv
rvfi_valid = None
rvfi_order = None
rvfi_insn = None
for netinfo in parse_vcd(argv[1]).values():
for net in netinfo['nets']:
print(net["hier"], net["name"])
if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_valid":
rvfi_valid = netinfo['tv']
if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_order":
rvfi_order = netinfo['tv']
if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_insn":
rvfi_insn = netinfo['tv']
assert len(rvfi_valid) == len(rvfi_order)
assert len(rvfi_valid) == len(rvfi_insn)
prog = list()
for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn):
if tv_valid[1] == '1':
prog.append((int(tv_order[1], 2), int(tv_insn[1], 2)))
with open("disasm.s", "w") as f:
for tv_order, tv_insn in sorted(prog):
if o == "-d":
mode_d = True
elif o == "--64":
mode_64 = True
else:
usage()
if len(args) != 1:
usage()
if mode_d:
tilelink_d_valid = None
tilelink_d_ready = None
tilelink_d_data = None
for netinfo in parse_vcd(args[0]).values():
for net in netinfo['nets']:
print(net["hier"], net["name"])
if net["hier"] in ["rvfi_testbench.wrapper", "testbench.uut"
] and net["name"] == "io_master_0_d_valid":
tilelink_d_valid = netinfo['tv']
if net["hier"] in ["rvfi_testbench.wrapper", "testbench.uut"
] and net["name"] == "io_master_0_d_ready":
tilelink_d_ready = netinfo['tv']
if net["hier"] in ["rvfi_testbench.wrapper", "testbench.uut"
] and net["name"] == "io_master_0_d_bits_data":
tilelink_d_data = netinfo['tv']
assert len(tilelink_d_valid) == len(tilelink_d_ready)
assert len(tilelink_d_valid) == len(tilelink_d_data)
def __init__(self, vcd_filename, timescale_divisor=1, start_cycle=0):
super(VcdCircuit, self).__init__()
logging.info("Parsing VCD file '%s'..." % vcd_filename)
self.parsed_vcd = parse_vcd(vcd_filename)
logging.info("Done parsing '%s'" % vcd_filename)
self.nodes = {}
working_bundles = {}
self.memory_depths = {} # TODO: refactor
for vcd_key, nets_tv_dict in self.parsed_vcd.iteritems():
for net_dict in nets_tv_dict['nets']:
parsed_node = VcdNode(vcd_key=vcd_key,
tv_list=scale_tv_list(nets_tv_dict['tv'],
timescale_divisor),
size=int(net_dict['size'], 10))
node_name = net_dict['hier'] + '.' + net_dict['name']
bracket_begin = node_name.rfind('[')
bracket_end = node_name.rfind(']')
if bracket_begin >= 0 and bracket_end >= 0 and bracket_begin < bracket_end:
# This deals with ModelSim VCDs which derp bundles into single bits.
node_name_stripped = node_name[:bracket_begin]
index = node_name[bracket_begin+1:bracket_end]
delim = index.find(':')
# TODO more graceful error handling
if delim >= 0:
begin_str = index[:delim]
end_str = index[delim+1:]
begin = int(begin_str)
end = int(end_str)
else:
begin = end = int(index)
if begin == end and parsed_node.size > 1:
# Special case for memory element "wires".
assert node_name not in self.nodes, "duplicate name: '%s': %s" % (node_name, net_dict)
self.memory_depths[node_name_stripped] = max(self.memory_depths.get(node_name_stripped, 1), begin+1)
self.nodes[node_name] = parsed_node
else:
if node_name_stripped not in working_bundles:
working_bundles[node_name_stripped] = {} # map high bit to VcdBundleElem
bundle = working_bundles[node_name_stripped]
assert begin >= end
assert begin not in bundle
bundle[begin] = VcdBundleElem(begin, end, parsed_node)
else:
assert node_name not in self.nodes, "duplicate name: '%s': %s" % (node_name, net_dict)
self.nodes[node_name] = parsed_node
logging.info("%i nodes found", len(self.nodes))
logging.debug("Nodes found: %s", self.nodes.keys())
# Post-process bundles
self.bundles = {}
for node_name, bundle in working_bundles.iteritems():
largest = None
prev = 0
sorted_elems = []
for begin_idx, bundle_elem in reversed(sorted(bundle.items())):
assert begin_idx == bundle_elem.high
if largest is None:
largest = bundle_elem.high
else:
assert bundle_elem.high == prev - 1, "prev %i, next high %i" % (prev, bundle_elem.high)
prev = bundle_elem.low
sorted_elems.append(bundle_elem)
assert prev == 0
bundle = VcdBundle(sorted_elems, largest)
assert node_name not in self.bundles
self.bundles[node_name] = bundle
logging.info("%i bundles found", len(self.bundles))
logging.debug("Bundles found: %s", self.bundles.keys())
logging.info("%i memories inferred", len(self.memory_depths))
self.initial_temporal_node = self.create_initial_temporal_node(start_cycle)
self.current_temporal_node = self.initial_temporal_node
self.width_dict = {}
for node_name, vcd_node in self.nodes.iteritems():
self.width_dict[node_name] = vcd_node.size
for node_name, vcd_bundle in self.bundles.iteritems():
assert node_name not in self.width_dict
self.width_dict[node_name] = vcd_bundle.size
self.current_view = ValueDictView(self, self.width_dict, self.memory_depths)
self.historical_view = ValueDictView(self, self.width_dict, self.memory_depths)
self.current_view.set_view(self.current_temporal_node.get_historical_state())
#!/usr/bin/env python
# coding: utf-8
import sys
from Verilog_VCD.Verilog_VCD import parse_vcd
import Verilog_VCD as vvcd
import json
file_name = sys.argv[1]
vcd = parse_vcd(file_name+'.vcd')
ts = vvcd.Verilog_VCD.get_timescale()
ts = int(''.join(filter(str.isdigit, ts)))
et = vvcd.Verilog_VCD.get_endtime()
def readGolden(golden):
Gwaves = {}
Gdata = {}
for i in golden["signal"]:
Gwaves[i["name"]] = i["wave"]
if i.get("data",None) != None:
Gdata[i["name"]] = i["data"]
return Gwaves,Gdata
goldenF = True if sys.argv[2] == "comp" else False
Gwaves = {}
Gdata = {}
if goldenF:
try:
json_file = open('code/golden.wf')
golden = eval(json_file.read())
#!/usr/bin/env python3
import os
from Verilog_VCD.Verilog_VCD import parse_vcd
lines = list()
for i in range(100):
fn = None
in1 = None
in2 = None
vcd = "muldivlen_cover/engine_0/trace%d.vcd" % i
if not os.path.isfile(vcd):
break
for netinfo in parse_vcd(vcd).values():
for net in netinfo['nets']:
if net["hier"] != "muldivlen":
continue
if net["name"] == "io_req_bits_fn":
fn = netinfo['tv'][0][1]
if net["name"] == "io_req_bits_in1":
in1 = netinfo['tv'][0][1]
if net["name"] == "io_req_bits_in2":
in2 = netinfo['tv'][0][1]
lines.append("%s %s %s" % (fn, in1, in2))
assert (len(lines) == 24)
for line in sorted(lines):
print(line)
#!/usr/bin/env python3
from Verilog_VCD.Verilog_VCD import parse_vcd
from os import system
rvfi_valid = None
rvfi_insn = None
for netinfo in parse_vcd('output.vcd').values():
for net in netinfo['nets']:
if net["hier"] == "testbench" and net["name"] == "rvfi_valid":
rvfi_valid = netinfo['tv']
if net["hier"] == "testbench" and net["name"] == "rvfi_insn":
rvfi_insn = netinfo['tv']
assert len(rvfi_valid) == len(rvfi_insn)
with open("disasm.s", "w") as f:
for tv_valid, tv_insn in zip(rvfi_valid, rvfi_insn):
assert tv_valid[0] == tv_insn[0]
if tv_valid[1] == '1':
print(".word 0x%08x" % int(tv_insn[1], 2), file=f)
system("riscv32-unknown-elf-gcc -c disasm.s")
system("riscv32-unknown-elf-objdump -d -M numeric,no-aliases disasm.o")
