# Create a 50MHz clock sequence for 50ms, 50% duty cycle
clk_seq = []
clk = 0
for i in range(8, 15000, 10):
clk = not clk
if (clk == True):
clk_seq.append([str(i), '1'])
else:
clk_seq.append([str(i), '0'])
# I/O and internal signal declaration
i_sigs0 = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["rst", "clk", "start"]}
o_sigs0 = {'D': 'o', 'del': 0, 'T': 'b', 'L': [0, 5], 'N': "state"}
o_sigs1 = {'D': 'o', 'del': 7, 'T': 'b', 'L': [0, 16], 'N': ["filt_out3", "filt_out1", "filt_out2"]}
o_sigs2 = {'D': 'o', 'del': 15, 'T': 'b', 'L': [0, 16], 'N': "filt_out0"}
o_sigs3 = {'D': 'o', 'del': 0, 'T': 'b', 'L': 1, 'N': "input_fifo_ready"}
o_sigs4 = {'D': 'o', 'del': 0, 'T': 'b', 'L': [0, 31], 'N': "sim_time"}
o_sigs5 = {'D': 'o', 'del': 0, 'T': 'b', 'L': [0, 31], 'N': "data_counter"}
o_sigs6 = {'D': 'o', 'del': 0, 'T': 'b', 'L': 1, 'N': "output_fifo_ready"}
# Define values for input signals
sim_sigs0 = {'D': 'sim', 'T': 'b', 'L': 1, 'N': "rst", 'V': [['0', '1'], ['5', '0']]}
sim_sigs1 = {'D': 'sim', 'T': 'b', 'L': 1, 'N': "clk", 'V': clk_seq}
sim_sigs2 = {'D': 'sim', 'T': 'b', 'L': 1, 'N': "start", 'V': [['0', '0'], ['6', '1']]}
code = getsourcelines(fsm_sim)
_toVHDL.toVHDL("fsm_sim", attributes, generics, i_sigs0, o_sigs0, o_sigs1, o_sigs2, o_sigs3, o_sigs4, o_sigs5, o_sigs6, sim_sigs0, sim_sigs1, sim_sigs2, code)
from inspect import *
import _toVHDL
reload(_toVHDL)
def debug_test():
b[3:2] = ctr
b[1] = ctr
# Design's atrributes
attributes = {"sign": '+'}
generics = {}
iosigs0 = {'D': 'i', 'T': 'b', 'L': 1, 'N': "ctr"}
iosigs1 = {'D': 'i', 'T': 'b', 'L': [7, 0], 'N': "a"}
iosigs2 = {'D': 'o', 'T': 'b', 'L': [7, 0], 'N': "b"}
code = getsourcelines(debug_test)
_toVHDL.toVHDL("debug_test", attributes, generics, iosigs0, iosigs1, iosigs2, code)
from inspect import *
import _toVHDL
reload(_toVHDL)
def clk_div():
def proc_0(clk, rst):
if rst == '0':
clk_div_25MHz_int = '0'
count_25MHz = 0
elif rising_edge(clk):
if count_25MHz == 1:
count_25MHz = 0
clk_div_25MHz_int = ~ clk_div_25MHz_int
else:
count_25MHz = count_25MHz + 1
clk_div_25MHz = clk_div_25MHz_int
# Design's atrributes
attributes = {"sign": '+', "FSM_STYLE": "lut", "MUX_EXTRACT": "yes"}
generics = { }
iosigs0 = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["rst", "clk"]}
iosigs1 = {'D': 'o', 'T': 'b', 'L': 1, 'N': "clk_div_25MHz"}
intrsigs0 = {'D': 'intr', 'T': 'b', 'L': 1, 'N': "clk_div_25MHz_int", 'V': '0'}
intrsigs1 = {'D': 'v', 'T': 'int', 'L': [0, 3], 'N': "count_25MHz", 'V': 0}
code = getsourcelines(clk_div)
_toVHDL.toVHDL("clk_div", attributes, generics, iosigs0, iosigs1, intrsigs0, intrsigs1, code)
nd = sqrt_write
x_out = sqrt_out
rdy = sqrt_ready
clk = clk
# Design's atrributes
attributes = {"sign": '-', "FSM_STYLE": "lut", "MUX_EXTRACT": "yes", "FPGA_DEV": "Virtex5"}
generics = {}
iosigs0 = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["rst", "clk", "t_cts", "t_dpr"]}
iosigs1 = {'D': 'o', 'T': 'b', 'L': 1, 'N': ["t_write", "t_read"]}
iosigs2 = {'D': 'i', 'T': 'b', 'L': [7, 0], 'N': "data_in"}
iosigs3 = {'D': 'o', 'T': 'b', 'L': [7, 0], 'N': "data_out"}
intrsigs0 = {'D': 'intr', 'T': 's', 'L': 1, 'N': "state", 'V': ["s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11"]}
intrsigs1 = {'D': 'intr', 'T': 'arrb', 'L': [[0, 9], [7, 0]], 'N': "window_data"}
intrsigs2 = {'D': 'intr', 'T': 'arrb', 'L': [[0, 2], [31, 0]], 'N': "sobel"}
intrsigs3 = {'D': 'intr', 'T': 'b', 'L': 1, 'N': ["sqrt_write", "sqrt_ready"]}
intrsigs4 = {'D': 'intr', 'T': 'b', 'L': [63, 0], 'N': "sqrt_in"}
intrsigs5 = {'D': 'intr', 'T': 'b', 'L': [24, 0], 'N': "sqrt_out"}
intrsigs6 = {'D': 'intr', 'T': 'b', 'L': [7, 0], 'N': "data_out_buf"}
intrsigs7 = {'D': 'intr', 'T': 'b', 'L': [23, 0], 'N': "zero_ext"}
intrsigs8 = {'D': 'v', 'T': 'int', 'L': [0, 15], 'N': "count"}
code = getsourcelines(sobel)
_toVHDL.toVHDL("sobel", attributes, generics, iosigs0, iosigs1, iosigs2, iosigs3, intrsigs0, intrsigs1, intrsigs2, intrsigs3, intrsigs4, intrsigs5, intrsigs6, intrsigs7, intrsigs8, code)
state = s2
elif state == s3:
if count >= 10:
sendnext = '1'
count = 0
state = smy0
elif count < 10:
count = count + 1
sendnext = '0'
state = s0
generics = {}
attributes = {"sign": '+', "PROC_SW": ["greth"], "FPGA_DEV": "Virtex5"}
i_sigs0 = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["clk", "ce2int"]}
i_sigs1 = {'D': 'i', 'T': 'b', 'L': [31, 0], 'N': ["dimem", "PORTA_in", "PORTB_in", "PORTC_in"]}
o_sigs0 = {'D': 'o', 'T': 'b', 'L': 1, 'N': ["sendnext", "sendfsmint", "rstFSMforsend"]}
o_sigs1 = {'D': 'o', 'T': 'b', 'L': [31, 0], 'N': ["PORTA_out", "PORTB_out", "PORTC_out"]}
int_sigs0 = {'D': 'intr', 'T': 'b', 'L': 1, 'N': ["m_rtr", "m_ack", "rst_fsm"]}
int_sigs1 = {'D': 'intr', 'T': 's', 'L': 1, 'N': "state", 'V': ["smy0", "smy1", "smy2", "smy1del", "s0", "s1", "s2", "s3"]}
int_sigs2 = {'D': 'intr', 'T': 'arrb', 'L': [[0, 10], [31, 0]], 'N': "ROM"}
int_sigs3 = {'D': 'v', 'T': 'int', 'L': [0, 15], 'N': "count"}
code = getsourcelines(HAL_FSM)
_toVHDL.toVHDL("HAL_FSM", attributes, generics, i_sigs0, i_sigs1, o_sigs0, o_sigs1, int_sigs0, int_sigs1, int_sigs2, int_sigs3, code)
state_trb = s4
elif h_read == '1':
t_cts = '0'
h_dpr = '1'
t_rec_buf = t_data_in
state_trb = s3
elif state_trb == s4:
t_cts = '1'
h_dpr = '0'
t_rec_buf = t_rec_buf
state_trb = s0
h_data_out = t_rec_buf
# Design's atrributes
attributes = {"sign": '+'}
generics = {'n': 8}
iosigs0 = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["rst", "clk", "h_write", "t_write", "h_read", "t_read"]}
iosigs1 = {'D': 'o', 'T': 'b', 'L': 1, 'N': ["h_cts", "t_cts", "h_dpr", "t_dpr"]}
iosigs2 = {'D': 'i', 'T': 'b', 'L': ["(n - 1)", 0], 'N': ["h_data_in", "t_data_in"]}
iosigs3 = {'D': 'o', 'T': 'b', 'L': ["(n - 1)", 0], 'N': ["h_data_out", "t_data_out"]}
intrsig0 = {'D': 'intr', 'T': 's', 'L': 1, 'N': ["state_hrb", "state_trb"], 'V': ["s0", "s1", "s2", "s3", "s4"]}
intrsig1 = {'D': 'intr', 'T': 'b', 'L': ["(n - 1)", 0], 'N': ["h_rec_buf", "t_rec_buf"], 'V': "00000000"}
data_flow_code = getsourcelines(simple2)
_toVHDL.toVHDL("simple2", attributes, generics, iosigs0, iosigs1, iosigs2, iosigs3, intrsig0, intrsig1, data_flow_code)
"D": "intr",
"T": "b",
"L": [7, 0],
"N": ["portd_avr", "porte_avr_unus", "ddrareg_out_int", "ddrbreg_out_int", "ddrcreg_out_int"],
}
intrsigs4 = {
"D": "intr",
"T": "b",
"L": [7, 0],
"N": ["ddrdreg_out_int", "ddrereg_out_int", "t_data_in_int", "t_data_out_int", "portc_buf", "gnb"],
}
intrsigs5 = {"D": "intr", "T": "b", "L": [1, 0], "N": ["porte_int", "pine_int", "porte_avr", "pine_avr"]}
code = getsourcelines(sobel_wrapper)
_toVHDL.toVHDL(
"sobel_wrapper",
attributes,
generics,
iosigs0,
iosigs1,
iosigs2,
intrsigs0,
intrsigs1,
intrsigs2,
intrsigs3,
intrsigs4,
intrsigs5,
code,
)
from inspect import *
import _toVHDL
import simple_func as s
reload(_toVHDL)
#reload(simple_func)
data_flow_code = getsourcelines(s)
#behavioral_code = getsourcelines(simple_proc)
_toVHDL.toVHDL("simple_func", s.xt, s.y1t, s.zt, s.z1t, s.clkt, s.st, data_flow_code)
x0t = {'D': 'i', 'T': 'b', 'L': [3, 0], 'N': ['x0', 'x1']}
y1t = {'D': 'i', 'T': 'b', 'L': [7, 0], 'N': ["y1", "y2"]}
clkt = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["clk_0", "rst"]}
zt = {'D': 'o', 'T': 'b', 'L': [3, 0], 'N': 'z'}
z0t = {'D': 'o', 'T': 'b', 'L': [3, 0], 'N': 'z0'}
testt = {'D': 'intr', 'T': 'b', 'L': 1, 'N': "test"}
z1t = {'D': 'intr', 'T': 'b', 'L': [3, 0], 'N': ['z1', "z2"], 'V': "1001"}
vart = {'D': 'intr', 'T': 'b', 'L': [3, 0], 'N': ["v1", "v2"], 'V': "1001"}
var2t = {'D': 'intr', 'T': 'int', 'L': [0, 3], 'N': ['mv', 'm0', 'i0', 'n0'], 'V': 3}
st = {'D': 'intr', 'T': 's', 'L': 1, 'N': "state", 'V': ["s0", "s1", "s2", "s3"]}
sig_int = {'D': 'intr', 'T': 'int', 'L': [-10,15], 'N': ["sig_int", "dfr", "z1"], 'V': 10}
sig_int2 = {'D': 'intr', 'T': 'int', 'L': [0,15], 'N': ["i", "m", "n"]}
arrb = {'D': 'intr', 'T': 'arrb', 'L': [[0, 2], [3, 0]], 'N': "arrb", 'V': ["101", "111", "0101"]}
arrbv = {'D': 'intr', 'T': 'arrb', 'L': [[0, 2], [3, 0]], 'N': "arrbv", 'V': ["111", "101", "1101"]}
arrv = {'D': 'intr', 'T': 'arrb', 'L': [[0, 2], [3, 0]], 'N': "arrv", 'V': ["111", "101", "1101"]}
arri = {'D': 'intr', 'T': 'arri', 'L': [[0, 2], [0, 15]], 'N': "arri", 'V': [10, 3, 8]}
arriv = {'D': 'intr', 'T': 'arri', 'L': [[0, 2], [0, 15]], 'N': "arriv", 'V': [20, 3, 8]}
data_flow_code = getsourcelines(simple)
#behavioral_code = getsourcelines(simple_proc)
_toVHDL.toVHDL("simple", attributes, generics, vart, var2t, sig_int, sig_int2, st, xt, x2t, y1t, zt, z1t, testt, clkt, x0t, z0t, arrb, arrv, arrbv, arri, arriv, data_flow_code)
from inspect import *
import _toVHDL
reload(_toVHDL)
def simple_filt():
filt_out = func_fir_filt(filt_in, filt_out_int, clk, rst, 8, "s", "6.2", -3.5, -64.0)
attributes = {"sign": '-'}
filt_in = {'D': 'i', 'T': 'b', 'L': [8, 0], 'N': "filt_in"}
clk_rst = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["clk", "rst"]}
filt_out = {'D': 'o', 'T': 'b', 'L': [18, 0], 'N': "filt_out"}
filt_out_int = {'D': 'intr', 'T': 'b', 'L': [18, 0], 'N': "filt_out_int"}
data_flow_code = getsourcelines(simple_filt)
_toVHDL.toVHDL("simple_filt", attributes, filt_in, filt_out, clk_rst, filt_out_int, data_flow_code)
h_data_out = portb_int
t_data_out = t_data_out_int
def struct_clk_div():
clk = clk_buf
rst = rst_buf
clk_div_25MHz = clk_div_25MHz_int
# Design's atrributes
attributes = {"sign": '+', "PROC_SW": ["greth"], "FPGA_DEV": "Virtex5"}
generics = {}
iosigs0 = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["clk", "rst", "rxd"]}
iosigs1 = {'D': 'o', 'T': 'b', 'L': 1, 'N': "txd"}
iosigs2 = {'D': 'o', 'T': 'b', 'L': [7, 0], 'N': "portc"}
intrsigs0 = {'D': 'intr', 'T': 'b', 'L': 1, 'N': ["clk_buf", "clk_div_25MHz_int", "clk_div_50MHz_int", "clk_div_100Hz_int", "rst_int", "gn"]}
intrsigs1 = {'D': 'intr', 'T': 'b', 'L': 1, 'N': ["t_cts_int", "t_dpr_int", "t_write_int", "t_read_int", "rst_buf", "txd_buf", "rxd_buf"]}
intrsigs2 = {'D': 'intr', 'T': 'b', 'L': [7, 0], 'N': ["porta_int", "portb_int", "portc_int", "portd_int", "porta_avr", "portb_avr", "portc_avr"]}
intrsigs3 = {'D': 'intr', 'T': 'b', 'L': [7, 0], 'N': ["portd_avr", "porte_avr_unus", "ddrareg_out_int", "ddrbreg_out_int", "ddrcreg_out_int"]}
intrsigs4 = {'D': 'intr', 'T': 'b', 'L': [7, 0], 'N': ["ddrdreg_out_int", "ddrereg_out_int", "t_data_in_int", "t_data_out_int", "portc_buf", "gnb"]}
intrsigs5 = {'D': 'intr', 'T': 'b', 'L': [1, 0], 'N': ["porte_int", "pine_int", "porte_avr", "pine_avr"]}
code = getsourcelines(proc_wrapper)
_toVHDL.toVHDL("proc_wrapper", attributes, generics, iosigs0, iosigs1, iosigs2, intrsigs0, intrsigs1, intrsigs2, intrsigs3, intrsigs4, intrsigs5, code)
state_trb = s4
elif h_read == '1':
t_cts = '0'
h_dpr = '1'
t_rec_buf = t_data_in
state_trb = s3
elif state_trb == s4:
t_cts = '1'
h_dpr = '0'
t_rec_buf = t_rec_buf
state_trb = s0
h_data_out = t_rec_buf
# Design's atrributes
attributes = {"sign": '+', "FSM_STYLE": "lut"}
generics = {'n': 8}
iosigs0 = {'D': 'i', 'T': 'b', 'L': 1, 'N': ["rst", "clk", "h_write", "t_write", "h_read", "t_read"]}
iosigs1 = {'D': 'o', 'T': 'b', 'L': 1, 'N': ["h_cts", "t_cts", "h_dpr", "t_dpr"]}
iosigs2 = {'D': 'i', 'T': 'b', 'L': ["(n - 1)", 0], 'N': ["h_data_in", "t_data_in"]}
iosigs3 = {'D': 'o', 'T': 'b', 'L': ["(n - 1)", 0], 'N': ["h_data_out", "t_data_out"]}
intrsigs0 = {'D': 'intr', 'T': 's', 'L': 1, 'N': ["state_hrb", "state_trb"], 'V': ["s0", "s1", "s2", "s3", "s4"]}
intrsigs1 = {'D': 'intr', 'T': 'b', 'L': ["(n - 1)", 0], 'N': ["h_rec_buf", "t_rec_buf"], 'V': "00000000"}
code = getsourcelines(bridge)
_toVHDL.toVHDL("bridge", attributes, generics, iosigs0, iosigs1, iosigs2, iosigs3, intrsigs0, intrsigs1, code)