def test_3():
ana = Analysis(input=root)
ana.gen_sources()
ana.set_target(target_name='fpga')
ctrl = ana.launch(debug=True)
# reset sequence
# the RNG takes 25000 cycles to start up, but we wait
# 10x longer to be extra sure (i.e., 25ms)
ctrl.set_param('cdf_rst', 1)
ctrl.set_reset(1)
ctrl.set_reset(0)
time.sleep(25e-3)
ctrl.set_param('cdf_rst', 0)
# run for some time (each second yields 10M points)
time.sleep(100)
# read out results
ctrl.stall_emu()
ctrl.refresh_param('vio_0_i')
cdfs = []
cdf_tot = int(ctrl.get_param('cdf_tot'))
for i in range(MIN_CDF, MAX_CDF + 1):
cdfs.append(int(ctrl.get_param(f'cdf_{numstr(i)}')))
# print results
print(f'cdf_tot: {cdf_tot}')
for i in range(MIN_CDF, MAX_CDF + 1):
print(f'{i}: {cdfs[i-MIN_CDF]/cdf_tot}')
def setup_target(test_name, test_root, target, simulator=None, synthesizer=None, viewer=None):
ana = Analysis(input=os.path.join(test_root, test_name),
build_root=os.path.join(BuildRoot.get_build_root, 'test_' + test_name),
simulator_name=simulator,
synthesizer_name=synthesizer,
viewer_name=viewer)
ana.gen_sources()
ana.set_target(target_name=target)
return ana
def main():
result_file = r'./results/dummy.vcd'
args = parse()
ana = Analysis(input=root) # create analysis object to host prototyping project
ana.set_target(target_name='fpga') # set the active target to 'fpga'
if args.gen_bitstream:
ana.gen_sources() # generate functional models
ana.build() # generate bitstream for project
ctrl_handle = ana.launch(debug=True) # start interactive control
ctrl_handle.set_reset(1) # reset simulation
ctrl_handle.setup_trace_unit(trigger_name='time',
trigger_operator='gt',
trigger_value=1e-9,
sample_decimation=0,
) # config & arm trace unit
#ctrl_handle.set_param('emu_ctrl_data', 10000000)
#ctrl_handle.set_param('emu_ctrl_mode', 3)
ctrl_handle.set_param('emu_ctrl_mode', 1)
ctrl_handle.set_reset(0) # start simulation
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.sleep_emu(1e-6)
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.sleep_emu(1e-6)
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.sleep_emu(1e-6)
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.sleep_emu(1e-6)
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.wait_on_and_dump_trace(result_file=result_file) # wait till trace buffer is full and dump to result file
ana.view(result_file=result_file) # view waveform
def main():
args = parse()
ana = Analysis(
input=root) # create analysis object to host prototyping project
ana.gen_sources() # generate functional models
ana.set_target(target_name='fpga') # set the active target to 'fpga'
if args.gen_bitstream:
ana.build() # generate bitstream for project
ctrl_handle = ana.launch(debug=True) # start interactive control
ctrl_handle.set_reset(1) # reset simulation
ctrl_handle.setup_trace_unit(trigger_name='time',
trigger_operator='gt',
trigger_value=5.5,
sample_decimation=800,
sample_count=16384) # config & arm trace unit
ctrl_handle.set_reset(0) # start simulation
ctrl_handle.wait_on_and_dump_trace(
) # wait till trace buffer is full and dump to result file
ana.view() # view waveform
def test_2():
ana = Analysis(input=root)
ana.gen_sources()
ana.set_target(target_name='fpga')
ana.build()
def test_1():
ana = Analysis(input=root, simulator_name='icarus')
ana.gen_sources()
ana.set_target(target_name='sim')
ana.simulate()