def write_register(self, register, value, **kwargs):
"""
Writes a register to the target
:param str register: The name of the register
:param int value: int value written to be written register
:raise angr.errors.ConcreteRegisterError
"""
# XMM/ST writes fail atm: https://github.com/radare/radare2/issues/13090
# Resolve some regs
if register in ['pc', 'sp', 'bp']:
l.debug('R2ConcreteTarget resolving %s', register)
register = self.r2.cmd('drn {}'.format(register)).strip()
l.debug('R2ConcreteTarget resolved to %s', register)
registers = self.r2.cmdj('drtj all')
#TODO: Implement xmm writes
if register not in registers:
error = "R2ConcreteTarget write_register unhandled reg name of {}".format(
register)
l.error(error)
raise SimConcreteRegisterError(error)
l.debug("R2ConcreteTarget write_register at %s value %x " %
(register, value))
self.r2.cmd('dr {}={}'.format(register, value))
# Validate write
if self.read_register(register) != value:
error = "R2ConcreteTarget write_register failed to correctly set register {}={}".format(
register, hex(value))
l.error(error)
raise SimConcreteRegisterError(error)
def write_register(self, register, value, **kwargs):
try:
l.debug("AvatarGDBConcreteTarget write_register at %s value %x "%(register,value))
res = self.target.write_register(register, value)
if not res:
l.warning("AvatarGDBConcreteTarget write_register failed reg %s value %x "%(register,value))
raise SimConcreteRegisterError("AvatarGDBConcreteTarget write_register failed reg %s value %x " % (register, value))
except Exception as e:
l.warning("AvatarGDBConcreteTarget write_register exception write reg %s value %x %s "%(register,value,e))
raise SimConcreteRegisterError("AvatarGDBConcreteTarget write_register exception write reg %s value %x %s " % (register, value, e))
def read_register(self, register, **kwargs):
""""
Reads a register from the target
:param str register: The name of the register
:return: int value of the register content
:rtype int
:raise angr.errors.ConcreteRegisterError in case the register doesn't exist or any other exception
"""
# Resolve some regs
if register in ['pc', 'sp', 'bp']:
l.debug('R2ConcreteTarget resolving %s', register)
register = self.r2.cmd('drn {}'.format(register)).strip()
l.debug('R2ConcreteTarget resolved to %s', register)
try:
l.debug("R2ConcreteTarget read_register at %s " % (register))
#registers = self.r2.cmdj('drtj all')
registers = get_all_registers(self.r2)
except Exception as e:
l.debug("R2ConcreteTarget read_register %s exception %s %s " %
(register, type(e).__name__, e))
raise SimConcreteRegisterError(
"R2ConcreteTarget can't read register %s exception %s" %
(register, e))
if register in registers:
import ipdb
ipdb.set_trace()
return registers[register]
# XMM
if register.startswith('xmm'):
try:
return (registers[register + 'l'] << 64) + registers[register +
'h']
except KeyError:
# This can be somewhat expected... xmm<n> wasn't found
l.warn('{} was not found.'.format(register))
pass
# R2 Currently also has a bug with floating point registers being shown incorrectly: https://github.com/radare/radare2/issues/13118
error = 'Unhandled register read of {}'.format(register)
l.error(error)
raise SimConcreteRegisterError(error)
def write_register(self, register, value, **kwargs):
"""
Writes a register to the target
:param str register: The name of the register
:param int value: int value written to be written register
:raise angr.errors.ConcreteRegisterError
"""
try:
rn = self.reg_table[register.lower()]
except KeyError:
raise SimConcreteRegisterError("Register %s does not exist", register)
try:
return self.jlink.register_write(rn, value)
except pylink.JLinkException:
l.exception("Error writing register %s", register)
def read_register(self,register,**kwargs):
""""
Reads a register from the target
:param str register: The name of the register
:return: int value of the register content
:rtype int
:raise angr.errors.ConcreteRegisterError in case the register doesn't exist or any other exception
"""
try:
rn = self.reg_table[register.lower()]
except KeyError:
raise SimConcreteRegisterError("Register %s does not exist", register)
try:
return self.jlink.register_read(rn)
except pylink.JLinkException:
l.exception("Error reading register %s", register)
def read_register(self, register, **kwargs):
""""
Reads a register from the target
:param str register: The name of the register
:return: int value of the register content
:rtype int
:raise angr.errors.ConcreteRegisterError in case the register doesn't exist or any other exception
"""
LOGGER.debug("RevengeConcreteTarget read_register at %s", register)
try:
return getattr(self._context, register)
except KeyError:
LOGGER.debug("RevengeConcreteTarget can't read_register %s",
register)
raise SimConcreteRegisterError(
"RevengeConcreteTarget can't read register %s", register)
def read_register(self,register,**kwargs):
try:
#l.debug("AvatarGDBConcreteTarget read_register at %s "%(register))
register_value = self.target.read_register(register)
except Exception as e:
#l.debug("AvatarGDBConcreteTarget read_register %s exception %s %s "%(register,type(e).__name__,e))
raise SimConcreteRegisterError("AvatarGDBConcreteTarget can't read register %s exception %s" % (register, e))
# when accessing xmm registers and ymm register gdb return a list of 4/8 32 bit values
# which need to be shifted appropriately to create a 128/256 bit value
if type(register_value) is list:
i = 0
result = 0
for val in register_value:
cur_val = val << i * 32
result |= cur_val
i += 1
return result
else:
return register_value
def write_register(self, register, value, **kwargs):
"""
Writes a register to the target
'pc' should be treated according to the architecture (eip,rip)
:param str register: The name of the register
:param int value: int value to be written to register
:raise angr.errors.ConcreteRegisterError:
"""
try:
value = "0x{0:x}".format(value)
self.s.write_register(register, value)
except Exception as e:
msg = (
"ZelosConcreteTarget can't write_register '%s', exception %s"
% (register, e)
)
l.debug(msg)
raise SimConcreteRegisterError(msg)
def read_register(self, register, **kwargs):
"""'
Reads a register from the target
'pc' should be treated according to the architecture (eip,rip)
:param str register: The name of the register
:return: int value of the register content
:rtype int
:raise angr.errors.ConcreteRegisterError: register doesn't exist
"""
try:
value = self.s.read_register(register)
value = int(value, 16) if value.startswith("0x") else int(value)
return value
except Exception as e:
msg = (
"ZelosConcreteTarget can't read_register '%s', exception %s"
% (register, e)
)
l.debug(msg)
raise SimConcreteRegisterError(msg)
