def cli(ctx, board, project_dir, verbose): """Clean the previous generated files.""" exit_code = SCons(project_dir).clean({ 'board': board, 'verbose': { 'all': verbose } }) ctx.exit(exit_code)
def cli(ctx, board, project_dir, verbose): """Verify the verilog code.""" exit_code = SCons(project_dir).verify({ 'board': board, 'verbose': { 'all': verbose } }) ctx.exit(exit_code)
def cli(ctx, all, top, nostyle, nowarn, warn, project_dir): """Lint the verilog code.""" exit_code = SCons(project_dir).lint({ 'all': all, 'top': top, 'nostyle': nostyle, 'nowarn': nowarn, 'warn': warn }) ctx.exit(exit_code)
def cli(ctx, board, fpga, pack, type, size): """Synthesize the bitstream.""" # Run scons exit_code = SCons().build({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }) ctx.exit(exit_code)
def cli(ctx, board, fpga, pack, type, size): """Bitstream timing analysis.""" # Run scons exit_code = SCons().time({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }) ctx.exit(exit_code)
def cli(ctx, device, board, fpga, pack, type, size): """Upload the bitstream to the FPGA.""" # Run scons exit_code = SCons().upload( { 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }, device) ctx.exit(exit_code)
def cli(ctx, device, board, fpga, pack, type, size, project_dir): """Upload the bitstream to the FPGA.""" drivers = Drivers() drivers.pre_upload() # Run scons exit_code = SCons(project_dir).upload( { 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }, device) drivers.post_upload() ctx.exit(exit_code)
def cli(ctx, board, serial_port, ftdi_id, sram, project_dir, verbose, verbose_yosys, verbose_nextpnr): """Upload the bitstream to the FPGA.""" drivers = Drivers() drivers.pre_upload() # Run scons exit_code = SCons(project_dir).upload( { 'board': board, 'verbose': { 'all': verbose, 'yosys': verbose_yosys, 'nextpnr': verbose_nextpnr } }, serial_port, ftdi_id, sram) drivers.post_upload() ctx.exit(exit_code)
def cli(ctx, board, fpga, pack, type, size, project_dir, verbose, verbose_yosys, verbose_pnr): """Bitstream timing analysis.""" # Run scons exit_code = SCons(project_dir).time({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack, 'verbose': { 'all': verbose, 'yosys': verbose_yosys, 'pnr': verbose_pnr } }) ctx.exit(exit_code)
def cli(ctx, board, fpga, pack, type, size, project_dir, verbose, verbose_yosys, verbose_pnr): """Synthesize the bitstream.""" # Run scons exit_code = SCons(project_dir).build({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack, 'verbose': { 'all': verbose, 'yosys': verbose_yosys, 'pnr': verbose_pnr } }) ctx.exit(exit_code)
def __init__(self): self.board="icezum" self.scons_engine=SCons(".") #Ahora mismo da problemas self.project=Project()
def cli(ctx): """Clean the previous generated files.""" exit_code = SCons().clean() ctx.exit(exit_code)
def __init__(self): self.board = "icezum" self.scons_engine = SCons(".") self.project = Project()
def cli(ctx, project_dir): """Clean the previous generated files.""" exit_code = SCons(project_dir).clean() ctx.exit(exit_code)
def cli(ctx, project_dir): """Launch the verilog simulation.""" exit_code = SCons(project_dir).sim() ctx.exit(exit_code)
def cli(ctx): """Verify the verilog code.""" exit_code = SCons().verify() ctx.exit(exit_code)
def cli(ctx): """Launch the verilog simulation.""" exit_code = SCons().sim() ctx.exit(exit_code)
def cli(ctx, project_dir): """Verify the verilog code.""" exit_code = SCons(project_dir).verify() ctx.exit(exit_code)