def architecture(self):
clkgen = ahe.clk_generator()
data = v_slv(32, 0)
@rising_edge(clkgen.clk)
def proc():
data << data + 1
self.f.write(str(value(data)) + '\n')
def architecture(self):
clkgen = ahe.clk_generator()
k_globals = klm_globals()
data = v_slv(32, 5)
dut = InputDelay(k_globals, Delay=5)
axprint = InputDelay_print(k_globals)
axprint.ConfigIn << dut.ConfigOut
k_globals.clk << clkgen.clk
d_source = dataSource(k_globals.clk)
dut.ConfigIn << d_source.DataOut
end_architecture()
def architecture(self):
counter = v_variable(v_slv(32))
max_cnt = v_variable(v_slv(32, 300))
clkgen = v_create(ahe.clk_generator())
cnt = Counter_cl()
@rising_edge(clkgen.clk)
def proc():
counter << counter + 1
cnt.count_to_max(max_cnt)
if cnt.isDone():
cnt.reset()
end_architecture()
def architecture(self):
clkgen = clk_generator()
k_globals = system_globals()
data = v_slv(32, 5)
dut = InputDelay(k_globals, Delay=5)
axprint = InputDelay_print(k_globals)
axprint.ConfigIn << dut.ConfigOut
k_globals.clk << clkgen.clk
mast = get_master(dut.ConfigIn)
@rising_edge(clkgen.clk)
def proc():
if mast:
mast << data
data << data + 1
end_architecture()
def architecture(self):
clkgen = ahe.clk_generator()
k_globals = klm_globals()
data = v_slv(32, 0)
dut = InputDelay(k_globals, Delay=5)
axprint = InputDelay_print(k_globals)
axprint.ConfigIn << dut.ConfigOut
k_globals.clk << clkgen.clk
d_source = dataSource(k_globals.clk)
dut.ConfigIn << d_source.DataOut
@rising_edge(clkgen.clk)
def proc():
data << data + 1
self.f.write(
str(value(data)) + ", " + str(value(d_source.DataOut.data)) +
", " + str(value(dut.ConfigOut.data)) + '\n')
end_architecture()
def clk_generator_test(OutputFolder):
clkgen = ahe.clk_generator()
return clkgen
