def run_main(prj: BagProject, args: argparse.Namespace) -> None:
if args.run_drc:
print('Running DRC')
success, log = prj.run_drc(args.lib, args.cell)
if success:
print('DRC passed!')
else:
print('DRC failed...')
print(f'log file: {log}')
elif args.run_lvs:
mode = 'LVS_RCX' if args.run_rcx else 'LVS'
print(f'Running {mode}')
success, log = prj.run_lvs(args.lib, args.cell, run_rcx=args.run_rcx)
if success:
print(f'{mode} passed!')
else:
print(f'{mode} failed...')
print(f'log file: {log}')
elif args.run_rcx:
print('Running RCX')
netlist, log = prj.run_rcx(args.lib, args.cell)
if netlist:
print('RCX passed!')
else:
print('RCX failed...')
print(f'log file: {log}')
else:
print('No operation specifiied, do nothing.')
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs: Mapping[str, Any] = read_yaml(args.specs)
log_level = LogLevel.WARN if args.quiet else LogLevel.INFO
prj.measure_cell(specs,
extract=args.extract,
force_sim=args.force_sim,
force_extract=args.force_extract,
gen_sch=args.gen_sch,
log_level=log_level,
fake=args.fake)
def test_dsn(bag_project: BagProject, dsn_specs: Dict[str, Any],
gen_output: bool, run_lvs: bool) -> None:
impl_lib: str = dsn_specs['impl_lib']
root_dir: str = dsn_specs['root_dir']
lay_str: str = dsn_specs.get('lay_class', '')
pytest_info: Dict[str, Path] = dsn_specs['pytest']
model_type: str = dsn_specs.get('model_type', 'SYSVERILOG')
root_path = Path(root_dir)
mod_type: DesignOutput = DesignOutput[model_type]
lay_db = bag_project.make_template_db(impl_lib)
bag_project.generate_cell(dsn_specs,
raw=True,
gen_lay=bool(lay_str),
gen_sch=True,
run_drc=False,
run_lvs=run_lvs,
run_rcx=False,
lay_db=lay_db,
gen_model=True)
if not gen_output:
for key, expect_path in pytest_info.items():
if key == 'test_id':
continue
out_path = root_path / key.replace('_', '.')
if not out_path.is_file():
raise ValueError(f'Cannot find output file: {out_path}')
if key.endswith('yaml'):
actual_dict = read_yaml(out_path)
expect_dict = read_yaml(expect_path)
assert actual_dict == expect_dict
elif key.endswith('gds'):
lay_map = get_gds_layer_map()
obj_map = get_gds_object_map()
grid = lay_db.grid
tr_colors = lay_db.tr_colors
expect_cv_list = read_gds(str(expect_path), lay_map, obj_map,
grid, tr_colors)
actual_cv_list = read_gds(str(out_path), lay_map, obj_map,
grid, tr_colors)
assert expect_cv_list == actual_cv_list
else:
if key.endswith('netlist'):
output_type = DesignOutput.CDL
else:
output_type = mod_type
actual = read_file(out_path)
expect = read_file(expect_path)
check_netlist(output_type, actual, expect)
def __init__(self,
bag_config_path: Optional[str] = None,
port: Optional[int] = None) -> None:
BagProject.__init__(self, bag_config_path, port)
# Init empty path variables to be set by user spec file
self.log_path = None
self.log_filename = 'output.log'
self.project_dir: Optional[Path] = None
self.scripts_dir: Optional[Path] = None
self.data_dir: Optional[Path] = None
self.content_dir: Optional[Path] = None
self.lsf_path = None
self.gds_path = None
BPG.run_settings.load_new_configuration(config_dict={})
def __init__(self, design_specs_fname):
"""
:param design_specs_fname: The main yaml file that should have some specific structure,
the template is given in ...
"""
self.bprj = BagProject()
self.design_specs_fname = design_specs_fname
self.ver_specs = read_yaml(self.design_specs_fname)
root_dir = self.ver_specs['root_dir']
self.gen_yamls_dir = os.path.join(root_dir, 'gen_yamls')
self.top_level_main_file = os.path.join(self.gen_yamls_dir, self.ver_specs['sim_spec_fname'])
self.gen_yamls_dir = os.path.join(self.gen_yamls_dir, 'swp_spec_files')
os.makedirs(self.gen_yamls_dir, exist_ok=True)
self.spec_range = self.ver_specs['spec_range']
self.param_choices_layout = self.break_hierarchy(self.ver_specs['params']['layout_params'])
self.param_choices_measurement = self.break_hierarchy(self.ver_specs['params']['measurements'])
# self.params contains the dictionary corresponding to the params part of the main yaml file where empty
# dicts are replaces with None
self.params = self.break_hierarchy(self.ver_specs['params'])
self.params_vec = {}
self.search_space_size = 1
for key, value in self.params.items():
if value is not None:
# self.params_vec contains keys of the main parameters and the corresponding search vector for each
self.params_vec[key] = np.arange(value[0], value[1], value[2]).tolist()
self.search_space_size = self.search_space_size * len(self.params_vec[key])
self.id_encoder = IDEncoder(self.params_vec)
self._unique_suffix = 0
self.temp_db = None
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs = read_yaml(args.specs)
prj.generate_cell(specs,
raw=args.raw,
gen_lay=args.gen_lay,
run_drc=args.run_drc,
gen_sch=args.gen_sch,
run_lvs=args.run_lvs,
run_rcx=args.run_rcx,
gen_lef=args.gen_lef,
flat=args.flat,
sim_netlist=args.gen_sim,
gen_hier=args.gen_hier,
gen_model=args.gen_mod,
gen_shell=args.gen_shell,
export_lay=args.export_lay,
gen_netlist=args.gen_netlist)
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs = read_yaml(args.specs)
ans = prj.measure_cell_old(specs,
gen_dut=args.gen_dut,
load_from_file=args.load_from_file,
extract=args.extract,
mismatch=args.mismatch)
print('measurement results:')
pprint.pprint(ans)
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
specs = read_yaml(args.specs)
lay_db = prj.make_template_db(specs['impl_lib']) if args.gen_lay else None
sch_db = prj.make_module_db(specs['impl_lib'])
cv_info = []
dut_params = specs['dut_params']
dut_netlist = prj.generate_cell(dut_params,
lay_db=lay_db,
sch_db=sch_db,
gen_lay=args.gen_lay,
gen_sch=args.gen_sch,
cv_info_out=cv_info,
run_rcx=args.run_rcx)
print(f'dut_netlist: {dut_netlist}')
wrapper_params = specs['wrapper_params']
prj.replace_dut_in_wrapper(wrapper_params['params'],
dut_params['impl_lib'], dut_params['impl_cell'])
generate_wrapper(sch_db,
wrapper_params,
cv_info,
dut_netlist,
gen_sch=args.gen_sch)
def run_main(prj: BagProject, gen_sch: bool = True, gen_cdl: bool = True, run_lvs: bool = True) \
-> None:
lib_name = 'AAA_XBASE_TEST'
fname = '00_mom_cap.yaml'
impl_cell = 'MOMCap_core'
fname_cdl = 'pvs_run/lvs_run_dir/' + lib_name + '/' + impl_cell + '/schematic.net'
params = read_yaml(Path('specs_test', 'xbase', fname))
db = TemplateDB(prj.grid, lib_name, prj=prj)
print('creating new template')
master = db.new_template(MOMCapCore, params)
print('creating batch layout')
# db.batch_layout([(master, '')], DesignOutput.LAYOUT)
db.batch_layout([(master, impl_cell)], DesignOutput.LAYOUT)
print('done')
if gen_sch or gen_cdl:
sch_db = ModuleDB(prj.tech_info, lib_name, prj=prj)
sch_master = sch_db.new_master(xbase__momcap_core, master.sch_params)
cv_info_list = []
print('creating schematic')
sch_db.batch_schematic([(sch_master, impl_cell)],
cv_info_out=cv_info_list)
print('schematic creation done')
if gen_cdl:
print('creating CDL netlist')
sch_db.batch_schematic([(sch_master, impl_cell)],
output=DesignOutput.CDL,
fname=fname_cdl,
cv_info_list=cv_info_list)
print('netlist creation done')
if run_lvs:
print('Running LVS ...')
lvs_passed, lvs_log = prj.run_lvs(lib_name,
impl_cell,
netlist=fname_cdl)
print('LVS log file:' + lvs_log)
if lvs_passed:
print('LVS passed!')
else:
print('LVS failed :(')
def run_main(prj: BagProject, args: Namespace):
specs_fname = Path(args.specs_fname)
io_cls = io_cls_dict[args.format]
specs = io_cls.load(str(specs_fname))
results = prj.simulate_cell(specs=specs,
gen_cell=args.gen_cell,
gen_wrapper=args.gen_wrapper,
gen_tb=args.gen_tb,
load_results=args.load_results,
extract=args.extract,
run_sim=args.run_sim)
if results is not None and args.dump:
out_tmp_file = Path(args.dump)
io_cls.save(results, out_tmp_file)
def __init__(self, design_specs_fname):
self.bprj = BagProject()
self.design_specs_fname = design_specs_fname
self.ver_specs = read_yaml(self.design_specs_fname)
root_dir = os.path.abspath(self.ver_specs['root_dir'])
self.gen_yamls_dir = os.path.join(root_dir, 'gen_yamls')
self.top_level_dir = os.path.join(self.gen_yamls_dir, 'top_level')
self.top_level_main_file = os.path.join(self.gen_yamls_dir,
'top_level.yaml')
os.makedirs(self.top_level_dir, exist_ok=True)
self.spec_range = self.ver_specs['spec_range']
self.param_choices_layout = self.break_hierarchy(
self.ver_specs['params']['layout_params'])
self.param_choices_measurement = self.break_hierarchy(
self.ver_specs['params']['measurements'])
# self.params contains the dictionary corresponding to the params part of the main yaml file where empty
# dicts are replaces with None
self.params = self.break_hierarchy(self.ver_specs['params'])
self.params_vec = {}
self.search_space_size = 1
for key, value in self.params.items():
if value is not None:
# self.params_vec contains keys of the main parameters and the corresponding search vector for each
self.params_vec[key] = np.arange(value[0], value[1],
value[2]).tolist()
self.search_space_size = self.search_space_size * len(
self.params_vec[key])
self.id_encoder = IDEncoder(self.params_vec)
self._unique_suffix = 0
self.temp_db = None
self.subckts_template = self.ver_specs['sub_system_sim']
self.subckts_yaml_dirs = dict()
self.subckts_main_file = dict()
for key in self.subckts_template.keys():
directory = os.path.join(self.gen_yamls_dir,
'subckt_{}'.format(key))
self.subckts_yaml_dirs[key] = directory
self.subckts_main_file[key] = directory + '.yaml'
os.makedirs(self.subckts_yaml_dirs[key], exist_ok=True)
def run_main(prj: BagProject, args: Namespace):
specs_fname = Path(args.specs_fname)
io_cls = io_cls_dict[args.format]
specs = io_cls.load(str(specs_fname))
results = prj.generate_cell(specs=specs,
gen_lay=args.gen_lay,
gen_sch=args.gen_sch,
run_lvs=args.lvs,
run_rcx=args.rcx,
use_cybagoa=True,
use_cache=args.use_cache,
save_cache=args.save_cache,
prefix=args.prefix,
suffix=args.suffix)
if results is not None and args.dump:
out_tmp_file = Path(args.dump)
io_cls.save(results, out_tmp_file)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from serdes_ec.layout.laygo.strongarm import SenseAmpStrongArm
if __name__ == '__main__':
with open('specs_test/serdes_ec/qdr_hybrid/strongarm.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
# bprj.generate_cell(block_specs, SenseAmpStrongArm)
# bprj.generate_cell(block_specs, SenseAmpStrongArm, gen_sch=True, run_lvs=True)
bprj.generate_cell(block_specs, SenseAmpStrongArm, gen_sch=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from serdes_ec.layout.qdr_hybrid.tapx import TapXSummer
if __name__ == '__main__':
with open('specs_test/serdes_ec/qdr_hybrid/tapx_summer.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, TapXSummer, debug=True)
# bprj.generate_cell(block_specs, TapXSummer, gen_sch=True, debug=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from analog_ec.layout.dac.rladder.core import ResLadderDAC
if __name__ == '__main__':
with open('specs_test/analog_ec/rdac/unit.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, ResLadderDAC, debug=True)
# bprj.generate_cell(block_specs, ResLadderDAC, gen_sch=True, run_lvs=True, debug=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from serdes_ec.layout.qdr_hybrid.datapath import RXDatapath
if __name__ == '__main__':
with open('specs_test/serdes_ec/qdr_hybrid/datapath.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
# bprj.generate_cell(block_specs, RXDatapath, debug=True)
bprj.generate_cell(block_specs, RXDatapath, gen_sch=True, debug=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from abs_templates_ec.routing.bias import BiasShieldCrossing
if __name__ == '__main__':
with open('specs_test/abs_templates_ec/routing/bias_crossing.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, BiasShieldCrossing, debug=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from abs_templates_ec.routing.fill import DecapFill
if __name__ == '__main__':
with open('specs_test/abs_templates_ec/routing/decap.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, DecapFill, debug=True)
# bprj.generate_cell(block_specs, DecapFill, gen_sch=True, debug=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from serdes_ec.layout.laygo.strongarm import SenseAmpStrongArm
if __name__ == '__main__':
with open('specs_test/serdes_ec/qdr_hybrid/strongarm.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, SenseAmpStrongArm)
# bprj.generate_cell(block_specs, SenseAmpStrongArm, gen_sch=True, run_lvs=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from serdes_ec.layout.analog.passives import CMLResLoad
if __name__ == '__main__':
with open('specs_test/serdes_ec/passives/cml_load.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, CMLResLoad, debug=True)
# bprj.generate_cell(block_specs, CMLResLoad, gen_sch=True, debug=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from digital_ec.layout.analog.inv import AnaInvChain
if __name__ == '__main__':
with open('specs_test/digital_ec/analog/inv_chain.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, AnaInvChain, debug=True)
# bprj.generate_cell(block_specs, AnaInvChain, gen_sch=True, debug=True)
# -*- coding: utf-8 -*-
from bag.core import BagProject
from bag.simulation.core import DesignManager
if __name__ == '__main__':
config_file = 'specs_test/nch_w0d5.yaml'
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
sim = DesignManager(bprj, config_file)
sim.test_layout(gen_sch=True)
help='True to pause using pdb.set_trace() after simulation is done')
args = parser.parse_args()
return args
def run_main(prj: BagProject, args: Namespace):
specs_fname = Path(args.specs_fname)
io_cls = io_cls_dict[args.format]
specs = io_cls.load(str(specs_fname))
results = prj.measure_cell(specs=specs,
gen_cell=args.gen_cell,
gen_wrapper=args.gen_wrapper,
gen_tb=args.gen_tb,
load_results=args.load_results,
extract=args.extract,
run_sims=args.run_sim)
if args.pause:
pdb.set_trace()
if results is not None and args.dump:
out_tmp_file = Path(args.dump)
io_cls.save(results, out_tmp_file)
if __name__ == '__main__':
args = parse_args()
local_dict = locals()
bprj = local_dict.get('bprj', BagProject())
run_main(bprj, args)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from serdes_ec.layout.tx.ser import Serializer32
if __name__ == '__main__':
with open('specs_test/serdes_ec/tx/ser32.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, Serializer32, debug=True)
# bprj.generate_cell(block_specs, Serializer32, gen_sch=True, debug=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from serdes_ec.layout.analog.cml import CMLAmpPMOS
if __name__ == '__main__':
with open('specs_test/serdes_ec/analog/cml_amp.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs, CMLAmpPMOS, debug=True)
# bprj.generate_cell(block_specs, CMLAmpPMOS, gen_sch=True, debug=True)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from analog_ec.layout.dac.rladder.top import RDACArray
if __name__ == '__main__':
with open('specs_test/analog_ec/rdac/array.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
# bprj.generate_cell(block_specs, RDACArray, debug=True, save_cache=True)
# bprj.generate_cell(block_specs, RDACArray, debug=True, use_cache=True)
bprj.generate_cell(block_specs, RDACArray, debug=True)
# bprj.generate_cell(block_specs, RDACArray, gen_lay=False, gen_sch=True)
async def async_generate_liberty(prj: BagProject, lib_config: Mapping[str, Any],
sim_config: Mapping[str, Any], cell_specs: Mapping[str, Any],
fake: bool = False, extract: bool = False,
force_sim: bool = False, force_extract: bool = False,
gen_all_env: bool = False, gen_sch: bool = False,
export_lay: bool = False, log_level: LogLevel = LogLevel.DEBUG
) -> None:
"""Generate liberty file for the given cells.
Parameters
----------
prj: BagProject
BagProject object to be able to generate things
lib_config : Mapping[str, Any]
library configuration dictionary.
sim_config : Mapping[str, Any]
simulation configuration dictionary.
cell_specs : Mapping[str, Any]
cell specification dictionary.
fake : bool
True to generate fake liberty file.
extract : bool
True to run extraction.
force_sim : bool
True to force simulation runs.
force_extract : bool
True to force extraction runs.
gen_all_env : bool
True to generate liberty files for all environments.
gen_sch : bool
True to generate schematics.
export_lay : bool
Use CAD tool to export layout.
log_level : LogLevel
stdout logging level.
"""
gen_specs_file: str = cell_specs['gen_specs_file']
scenario: str = cell_specs.get('scenario', '')
gen_specs: Mapping[str, Any] = read_yaml(gen_specs_file)
impl_lib: str = gen_specs['impl_lib']
impl_cell: str = gen_specs['impl_cell']
lay_cls: str = gen_specs['lay_class']
dut_params: Mapping[str, Any] = gen_specs['params']
name_prefix: str = gen_specs.get('name_prefix', '')
name_suffix: str = gen_specs.get('name_suffix', '')
gen_root_dir: Path = Path(gen_specs['root_dir'])
lib_root_dir = gen_root_dir / 'lib_gen'
sim_precision: int = sim_config['precision']
dsn_options = dict(
extract=extract,
force_extract=force_extract,
gen_sch=gen_sch,
log_level=log_level,
)
log_file = str(lib_root_dir / 'lib_gen.log')
sim_db = prj.make_sim_db(lib_root_dir / 'dsn', log_file, impl_lib, dsn_options=dsn_options,
force_sim=force_sim, precision=sim_precision, log_level=log_level)
dut = await sim_db.async_new_design(impl_cell, lay_cls, dut_params, export_lay=export_lay,
name_prefix=name_prefix, name_suffix=name_suffix)
environments: Mapping[str, Any] = lib_config['environments']
nom_voltage_type: str = environments['nom_voltage_type']
name_format: str = environments['name_format']
voltage_precision: int = environments['voltage_precision']
sim_env_list: List[Mapping[str, Any]] = environments['sim_envs']
if not gen_all_env:
sim_env_list = [sim_env_list[0]]
voltage_fmt = '{:.%df}' % voltage_precision
lib_file_base_name = f'{impl_cell}_{scenario}' if scenario else impl_cell
for sim_env_config in sim_env_list:
sim_env: str = sim_env_config['sim_env']
voltages: Mapping[str, float] = sim_env_config['voltages']
vstr_table = {k: voltage_fmt.format(v).replace('.', 'p') for k, v in voltages.items()}
sim_env_name = name_format.format(sim_env=sim_env, **vstr_table)
lib_file_name = f'{lib_file_base_name}_{sim_env_name}'
cur_lib_config = dict(**lib_config)
cur_lib_config.pop('environments')
# setup lib config
temperature = get_corner_temp(sim_env)[1]
env_config = dict(
name=sim_env_name,
bag_name=sim_env,
process=1.0,
temperature=temperature,
voltage=voltages[nom_voltage_type],
)
cur_lib_config['voltages'] = voltages
cur_lib_config['sim_envs'] = [env_config]
lib = Library(f'{impl_cell}_{sim_env_name}', cur_lib_config)
out_file = gen_root_dir / f'{lib_file_name}.lib'
lib_data, mm_specs, cur_work_dir = get_cell_info(lib, impl_cell, cell_specs,
lib_root_dir, voltage_fmt)
mm_specs['fake'] = fake
mm_specs['sim_env_name'] = sim_env_name
for key in ['tran_tbm_specs', 'buf_params', 'in_cap_search_params', 'out_cap_search_params',
'seq_search_params', 'seq_delay_thres']:
mm_specs[key] = sim_config[key]
mm = sim_db.make_mm(LibertyCharMM, mm_specs)
sim_db.log(f'Characterizing {lib_file_name}.lib')
char_results = await sim_db.async_simulate_mm_obj('lib_char', cur_work_dir, dut, mm)
pin_data = char_results.data
_add_cell(lib, lib_data, pin_data)
lib.generate(out_file)
# compute schematic parameters
self._sch_params = dict(
lch=lch,
w_dict=w_dict,
th_dict=th_dict,
seg_dict=seg_dict,
stack_dict=stack_dict,
dum_info=self.get_sch_dummy_info(),
)
if __name__ == '__main__':
with open('specs_test/vco_core.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
bprj.generate_cell(block_specs,
VCOCore,
gen_sch=False,
run_lvs=False,
use_cybagoa=True)
# bprj.generate_cell(block_specs, VCOCore, gen_sch=True, run_lvs=False, use_cybagoa=True)
def run_main(prj: BagProject, args: argparse.Namespace) -> None:
prj.remove_gds_labels(args.in_file, args.out_file, args.specs_file)
# -*- coding: utf-8 -*-
import yaml
from bag.core import BagProject
from serdes_ec.layout.qdr_hybrid.amp import IntegAmp
if __name__ == '__main__':
with open('specs_test/serdes_ec/qdr_hybrid/integ_amp.yaml', 'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
# bprj.generate_cell(block_specs, IntegAmp, debug=True)
bprj.generate_cell(block_specs, IntegAmp, gen_sch=True, debug=True)
