def __init__(self, src="uhd", dst="uhd", in_rate=2e6, out_rate=2e6, extra=None): super(tag_emulate, self).__init__() uhd = dst == "uhd" if uhd: dst = None self._bin_src = binary_src.binary_src(out_rate, encode="manchester", idle_bit=0) parser = Parser(extra) self._tag = parser.get_tag(self._bin_src.set_bits) # Do not record here self._dec = decoder.decoder(src=src, dst=None, reader=True, tag=False, samp_rate=in_rate, emulator=self._tag) self.connect(self._dec) self._mult = multiplier.multiplier(samp_rate=out_rate) self.connect(self._bin_src, self._mult) if uhd: # active load modulation self._real = blocks.complex_to_real(1) self._thres = blocks.threshold_ff(0.02, 0.1, 0) self._r2c = blocks.float_to_complex(1) self._sink = usrp_sink.usrp_sink(out_rate) self.connect(self._mult, self._real, self._thres, self._r2c, self._sink) elif dst: self._sink = record.record(dst, out_rate) self.connect(self._mult, self._sink) else: self._sink = blocks.null_sink(gr.sizeof_gr_complex) self.connect(self._mult, self._sink)
def __init__(self, src="uhd", dst="uhd", in_rate=2e6, out_rate=2e6, extra=None): super(reader_emulate, self).__init__() uhd = dst == "uhd" if uhd: dst = None self._bin_src = binary_src.binary_src(out_rate, encode="miller", idle_bit=1, repeat=[0, 1, 1, 0, 0, 1, 0]) # repeat REQA parser = Parser(extra) self._reader = parser.get_reader(self._bin_src.set_bits) # Do not record this self._dec = decoder.decoder(src=src, dst=None, reader=False, tag=True, samp_rate=in_rate, emulator=self._reader) self.connect(self._dec) self._mult = multiplier.multiplier(samp_rate=out_rate) self.connect(self._bin_src, self._mult) if uhd: self._sink = usrp_sink.usrp_sink(out_rate) elif dst: self._sink = record.record(dst, out_rate) else: self._sink = blocks.null_sink(gr.sizeof_gr_complex) self.connect(self._mult, self._sink)