def add_modules(self):
""" Add the modules for later usage """
from importlib import reload
g = reload(__import__(OPTS.delay_chain))
self.mod_delay_chain = getattr(g, OPTS.delay_chain)
g = reload(__import__(OPTS.replica_bitcell))
self.mod_replica_bitcell = getattr(g, OPTS.replica_bitcell)
self.bitcell = self.replica_bitcell = self.mod_replica_bitcell()
self.add_mod(self.bitcell)
# This is the replica bitline load column that is the height of our array
self.rbl = bitcell_array(name="bitline_load",
cols=1,
rows=self.bitcell_loads)
self.add_mod(self.rbl)
# FIXME: The FO and depth of this should be tuned
self.delay_chain = self.mod_delay_chain([self.delay_fanout] *
self.delay_stages)
self.add_mod(self.delay_chain)
self.inv = pinv()
self.add_mod(self.inv)
self.access_tx = ptx(tx_type="pmos")
self.add_mod(self.access_tx)
def create_modules(self):
""" create module """
self.replica_bitcell = self.mod_replica_bitcell()
self.add_mod(self.replica_bitcell)
# This is the replica bitline load column that is the same height as our array
self.bitline_load = bitcell_array(name="bitline_load",
cols=1,
rows=self.rows)
self.add_mod(self.bitline_load)
# FIXME: This just creates 3 1x inverters
self.delay_chain = self.mod_delay_chain("delay_chain", [1, 1, 1])
self.add_mod(self.delay_chain)
self.inv = pinv(name="RBL_inv", nmos_width=drc["minwidth_tx"])
self.add_mod(self.inv)
# These aren't for instantiating, but we use them to get the dimensions
self.poly_contact = contact(layer_stack=("poly", "contact", "metal1"))
self.m1m2_via = contact(layer_stack=("metal1", "via1", "metal2"))
self.m2m3_via = contact(layer_stack=("metal2", "via2", "metal3"))
self.nor = nor_2(name="replica_bitline_nor2",
nmos_width=drc["minwidth_tx"])
self.add_mod(self.nor)
self.access_tx = ptx(width=drc["minwidth_tx"], mults=1, tx_type="pmos")
self.add_mod(self.access_tx)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
debug.info(2, "Testing 4x4 array for 6t_cell")
a = bitcell_array.bitcell_array(name="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
debug.info(
2,
"Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell"
)
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 2
OPTS.num_w_ports = 2
a = bitcell_array.bitcell_array(name="pbitcell_array_Rport_edge",
cols=4,
rows=4)
self.local_check(a)
debug.info(
2,
"Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell"
)
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 0
OPTS.num_w_ports = 2
a = bitcell_array.bitcell_array(name="pbitcell_array_Wport_edge",
cols=4,
rows=4)
self.local_check(a)
debug.info(
2,
"Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell"
)
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
a = bitcell_array.bitcell_array(name="pbitcell_array_RWport_edge",
cols=4,
rows=4)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import bitcell_array
debug.info(2, "Testing 3x3 array for 6t_cell")
a = bitcell_array.bitcell_array(name="bitcell_array", cols=1, rows=1)
OPTS.check_lvsdrc = True
self.local_check(a)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
a = bitcell_array.bitcell_array(name="bitcell_1rw_1r_array",
cols=4,
rows=4)
self.local_check(a)
globals.end_openram()
def runTest(self):
globals.init_AMC("config_20_{0}".format(OPTS.tech_name))
global calibre
import calibre
OPTS.check_lvsdrc = False
import bitcell_array
debug.info(2, "Testing 64x4 array for 6t_cell")
a = bitcell_array.bitcell_array(name="bitcell_array", cols=4, rows=8)
self.local_check(a)
# return it back to it's normal state
OPTS.check_lvsdrc = True
globals.end_AMC()
def create_modules(self):
""" Create modules for later instantiation """
self.bitcell = self.replica_bitcell = self.mod_replica_bitcell()
self.add_mod(self.bitcell)
# This is the replica bitline load column that is the height of our array
self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.rows)
self.add_mod(self.rbl)
self.delay_chain = self.mod_delay_chain([1, 1, 1])
self.add_mod(self.delay_chain)
self.inv = pinv()
self.add_mod(self.inv)
self.access_tx = ptx(tx_type="pmos")
self.add_mod(self.access_tx)
def create_modules(self):
""" Create modules for later instantiation """
self.bitcell = self.replica_bitcell = self.mod_replica_bitcell()
self.add_mod(self.bitcell)
# This is the replica bitline load column that is the height of our array
self.rbl = bitcell_array(name="bitline_load",
cols=1,
rows=self.bitcell_loads)
self.add_mod(self.rbl)
# FIXME: The FO and depth of this should be tuned
self.delay_chain = self.mod_delay_chain([4] * self.FO4_stages)
self.add_mod(self.delay_chain)
self.inv = pinv()
self.add_mod(self.inv)
self.access_tx = ptx(tx_type="pmos")
self.add_mod(self.access_tx)
def __init__(self,
name,
word_size,
measured_WL_pos,
extra=1,
strength=None):
design.design.__init__(self, name)
self.word_size = word_size
self.add_pin("sel")
self.add_pin("clk")
self.add_pin("wl")
self.add_pin("vdd")
self.add_pin("gnd")
if strength == None:
self.nand_size, self.inv_size = self.logic_effort_sizing(word_size)
else:
self.nand_size = 2
self.inv_size = strength
seg_size = self.word_size / extra
self.inv_size = self.inv_size / extra
driver = p_wordline_driver.wordline_driver(name="Wordline_driver",
rows=1)
array = bitcell_array.bitcell_array(name="bitcell_array",
cols=seg_size,
rows=1)
array_offset = vector(driver.width + 6 * drc["minwidth_metal1"], 0)
driver_to_array = 6 * drc["minwidth_metal1"]
# adding metal to just test the wire RC
start = array_offset + array.WL_positions[0]
end = start + vector(array.width, 0)
#print "array.width",array.width
self.add_path(("metal1"), [start, end])
#"""
if extra > 1:
for seg in range(1, extra):
seg_driver_width = driver.driver.width
#print seg," array and dirver"
arary_i_offset = array_offset + vector(
(array.width + 2 * driver_to_array + seg_driver_width) *
(seg - 1), 0)
#print "arary_i_offset",arary_i_offset
self.add_inst(name="array{0}".format(seg),
mod=array,
offset=arary_i_offset)
temp = []
for i in range(seg_size):
temp.append("bl{0}".format(i + (seg - 1) * seg_size))
temp.append("br{0}".format(i + (seg - 1) * seg_size))
temp = temp + ["wl", "vdd", "gnd"]
self.connect_inst(temp)
extra_driver_offset = arary_i_offset + vector(
driver_to_array + array.width, 0)
driver.add_extra_driver(extra_driver_offset)
#print "extra_driver_offset",extra_driver_offset
WL_offset = arary_i_offset + array.WL_positions[-1]
driver.route_extra_WL(WL_offset)
arary_i_offset = array_offset + vector(
(array.width + 2 * driver_to_array + seg_driver_width) *
seg, 0)
WL_offset = arary_i_offset + array.WL_positions[0]
vdd_offset = arary_i_offset + array.vdd_positions[-1]
gnd_offset = arary_i_offset + array.gnd_positions[-1]
if seg != extra - 1:
driver.extend_extra_WL(WL_offset)
driver.extend_extra_vdd(vdd_offset)
driver.extend_extra_gnd(gnd_offset)
else:
self.add_inst(name="array", mod=array, offset=array_offset)
temp = []
for i in range(seg_size):
temp.append("bl{0}".format(i))
temp.append("br{0}".format(i))
temp = temp + ["wl", "vdd", "gnd"]
self.connect_inst(temp)
#"""
self.add_mod(array)
self.add_mod(driver)
self.add_inst(name="wordline_driver", mod=driver, offset=[0, 0])
temp = ['sel', 'wl', 'clk', 'vdd', 'gnd']
self.connect_inst(temp)
self.add_label(text="clk",
layer="metal1",
offset=driver.clk_positions[0])
self.add_label(text="sel",
layer="metal2",
offset=driver.decode_out_positions[0])
#self.add_label(text="wl",
# layer="metal1",
# offset=driver.WL_positions[0])
offset = array_offset + vector(measured_WL_pos * array.width,
array.WL_positions[0].y)
self.add_label(text="wl", layer="metal1", offset=offset)
self.add_label(text="vdd",
layer="metal1",
offset=driver.vdd_positions[0])
self.add_label(text="gnd",
layer="metal1",
offset=driver.gnd_positions[0])
start = [
driver.WL_positions[0].x + drc["minwidth_metal1"],
driver.WL_positions[0].y + drc["minwidth_metal1"]
]
end = [
driver.width + 6 * drc["minwidth_metal1"], array.WL_positions[0].y
]
self.add_path(layer=("metal1"), coordinates=[start, end], offset=start)
start = driver.vdd_positions[0]
start = [start[0], start[1] + 0.5 * drc["minwidth_metal1"]]
end = [end[0], start[1]]
self.add_path(layer=("metal1"), coordinates=[start, end], offset=start)
start = driver.gnd_positions[0]
start = [start[0], start[1] + 0.5 * drc["minwidth_metal1"]]
end = [end[0], start[1]]
self.add_path(layer=("metal1"), coordinates=[start, end], offset=start)
