def digitiser_stop():
print 'Stopping digitiser'
fdig = KatcpClientFpga(dhost)
if fdig.is_running():
fdig.test_connection()
fdig.get_system_information()
fdig.registers.control.write(gbe_txen = False)
fdig.deprogram()
fdig.disconnect()
def digitiser_start(dig_tx_tuple):
fdig = KatcpClientFpga(dhost)
fdig.deprogram()
stime = time.time()
print 'Programming digitiser',
sys.stdout.flush()
fdig.upload_to_ram_and_program(dbof)
print time.time() - stime
fdig.test_connection()
fdig.get_system_information()
# stop sending data
fdig.registers.control.write(gbe_txen = False)
# start the local timer on the test d-engine - mrst, then a fake sync
fdig.registers.control.write(mrst = 'pulse')
fdig.registers.control.write(msync = 'pulse')
# the all_fpgas have tengbe cores, so set them up
ip_bits = dip_start.split('.')
ipbase = int(ip_bits[3])
mac_bits = dmac_start.split(':')
macbase = int(mac_bits[5])
for ctr in range(0,4):
mac = '%s:%s:%s:%s:%s:%d' % (mac_bits[0], mac_bits[1], mac_bits[2], mac_bits[3], mac_bits[4], macbase + ctr)
ip = '%s.%s.%s.%d' % (ip_bits[0], ip_bits[1], ip_bits[2], ipbase + ctr)
fdig.tengbes['gbe%d' % ctr].setup(mac=mac, ipaddress=ip, port=7777)
for gbe in fdig.tengbes:
gbe.tap_start(True)
# set the destination IP and port for the tx
txaddr = dig_tx_tuple[0]
txaddr_bits = txaddr.split('.')
txaddr_base = int(txaddr_bits[3])
txaddr_prefix = '%s.%s.%s.' % (txaddr_bits[0], txaddr_bits[1], txaddr_bits[2])
print 'digitisers sending to: %s%d port %d' % (txaddr_prefix, txaddr_base + 0, dig_tx_tuple[2])
fdig.write_int('gbe_iptx0', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 0)))
fdig.write_int('gbe_iptx1', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 1)))
fdig.write_int('gbe_iptx2', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 2)))
fdig.write_int('gbe_iptx3', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 3)))
fdig.write_int('gbe_porttx', dig_tx_tuple[2])
fdig.registers.control.write(gbe_rst=False)
# enable the tvg on the digitiser and set up the pol id bits
fdig.registers.control.write(tvg_select0=True)
fdig.registers.control.write(tvg_select1=True)
fdig.registers.id2.write(pol1_id=1)
# start tx
print 'Starting dig TX...',
sys.stdout.flush()
fdig.registers.control.write(gbe_txen=True)
print 'done.'
sys.stdout.flush()
fdig.disconnect()
default=False,
help='reset all counters at script startup')
args = parser.parse_args()
polltime = args.polltime
xeng_hosts = args.hosts.lstrip().rstrip().replace(' ', '').split(',')
xeng_hosts = ['roach020921', 'roach020927', 'roach020919', 'roach020925',
'roach02091a', 'roach02091e', 'roach020923', 'roach020924']
# create the devices and connect to them
ffpgas = []
for host in xeng_hosts:
xeng_fpga = KatcpClientFpga(host)
xeng_fpga.get_system_information()
if args.rstcnt:
xeng_fpga.registers.control.write(cnt_rst='pulse')
ffpgas.append(xeng_fpga)
def get_fpga_data(fpga):
data = {}
for pol in [0,1]:
data['rx_cnt%i' % pol] = fpga.device_by_name('rx_cnt%i' % pol).read()['data']['reg']
data['rx_err_cnt%i' % pol] = fpga.device_by_name('rx_err_cnt%i' % pol).read()['data']['reg']
return data
data = get_fpga_data(ffpgas[0])
reg_names = data.keys()
reg_names.sort()
rxhosts = ['roach020826', 'roach02070f', 'roach020828', 'roach02082c',
'roach02064f', 'roach02064a', 'roach020815', 'roach020650',
'roach02080f', 'roach020813', 'roach020712', 'roach02082d',
'roach02081c', 'roach020637', 'roach02081e', 'roach02064b',
'roach02070f', 'roach02082c', 'roach020818', 'roach02070e']
fchan_per_x = 128
xengines
f = KatcpClientFpga('roach020921')
f.get_system_information()
#
#import corr, struct
#f = corr.katcp_wrapper.FpgaClient('roach020921')
#time.sleep(0.3)
#sd = f.snapshot_get('snap_reord0_ss', circular_capture=True, man_trig=True)
#up = struct.unpack('>2048Q', sd['data'])
#for ctr in range(0, 2048, 2):
# print ctr, ':',
# w1 = up[ctr]
# w2 = up[ctr+1]
# sync = (w1 >> 63) & 0x01
# data = (w1 >> 31) & 0xffffffff
# valid = (w1 >> 30) & 0x01
# dtime = ((w1 & (pow(2,30)-1)) << 12) & ((w2 >> 46) & (pow(2,18)-1))
fpga.deprogram()
ftuple = [(fdig, dfpg)]
ftuple.extend([(fpga, ffpg) for fpga in ffpgas])
ftuple.extend([(fpga, xfpg) for fpga in xfpgas])
stime = time.time()
print('Programming: ',
sys.stdout.flush()
misc.program_fpgas(ftuple, timeout=45)
print(time.time() - stime
ftuple = None
for fpga in all_fpgas:
fpga.test_connection()
fpga.get_system_information()
if setup_gbe:
# stop sending data
fdig.registers.control.write(gbe_txen=False)
for fpga in ffpgas:
fpga.registers.control.write(gbe_txen=False)
for fpga in xfpgas:
fpga.registers.control.write(gbe_txen=False)
# pulse the cores reset lines from False to True
fdig.registers.control.write(gbe_rst = False)
for fpga in ffpgas:
fpga.registers.control.write(gbe_rst = False)
for fpga in xfpgas:
fpga.registers.control.write(gbe_rst = False)
# fdig.registers.control.write(gbe_rst = True)
# for fpga in ffpgas:
