def write_register(_cs, reg_name, reg_value, cpu_thread=0):
reg = _cs.Cfg.REGISTERS[reg_name]
rtype = reg['type']
if RegisterType.PCICFG == rtype:
b = int(reg['bus'], 16)
d = int(reg['dev'], 16)
f = int(reg['fun'], 16)
o = int(reg['offset'], 16)
size = int(reg['size'], 16)
if 1 == size: _cs.pci.write_byte(b, d, f, o, reg_value)
elif 2 == size: _cs.pci.write_word(b, d, f, o, reg_value)
elif 4 == size: _cs.pci.write_dword(b, d, f, o, reg_value)
elif 8 == size:
_cs.pci.write_dword(b, d, f, o, (reg_value & 0xFFFFFFFF))
_cs.pci.write_dword(b, d, f, o + 4, (reg_value >> 32 & 0xFFFFFFFF))
elif RegisterType.MMCFG == rtype:
mmio.write_mmcfg_reg(_cs, int(reg['bus'], 16), int(reg['dev'], 16),
int(reg['fun'], 16), int(reg['offset'], 16),
int(reg['size'], 16), reg_value)
elif RegisterType.MMIO == rtype:
mmio.write_MMIO_BAR_reg(_cs, reg['bar'], int(reg['offset'], 16),
reg_value, int(reg['size'], 16))
elif RegisterType.MSR == rtype:
eax = (reg_value & 0xFFFFFFFF)
edx = ((reg_value >> 32) & 0xFFFFFFFF)
_cs.msr.write_msr(cpu_thread, int(reg['msr'], 16), eax, edx)
elif RegisterType.PORT == rtype:
port = int(reg['port'], 16)
size = int(reg['size'], 16)
_cs.io._write_port(port, reg_value, size)
elif RegisterType.IOBAR == rtype:
iobar = chipsec.hal.iobar(_cs)
iobar.write_IO_BAR_reg(reg['bar'], int(reg['offset'], 16), reg_value)
def write_register( _cs, reg_name, reg_value, cpu_thread=0 ):
reg = _cs.Cfg.REGISTERS[ reg_name ]
rtype = reg['type']
if RegisterType.PCICFG == rtype:
b = int(reg['bus'],16)
d = int(reg['dev'],16)
f = int(reg['fun'],16)
o = int(reg['offset'],16)
size = int(reg['size'],16)
if 1 == size: _cs.pci.write_byte( b, d, f, o, reg_value )
elif 2 == size: _cs.pci.write_word( b, d, f, o, reg_value )
elif 4 == size: _cs.pci.write_dword( b, d, f, o, reg_value )
elif 8 == size:
_cs.pci.write_dword( b, d, f, o, (reg_value & 0xFFFFFFFF) )
_cs.pci.write_dword( b, d, f, o + 4, (reg_value>>32 & 0xFFFFFFFF) )
elif RegisterType.MMCFG == rtype:
mmio.write_mmcfg_reg( _cs, int(reg['bus'],16), int(reg['dev'],16), int(reg['fun'],16), int(reg['offset'],16), int(reg['size'],16), reg_value )
elif RegisterType.MMIO == rtype:
mmio.write_MMIO_BAR_reg( _cs, reg['bar'], int(reg['offset'],16), reg_value, int(reg['size'],16) )
elif RegisterType.MSR == rtype:
eax = (reg_value & 0xFFFFFFFF)
edx = ((reg_value >> 32) & 0xFFFFFFFF)
_cs.msr.write_msr( cpu_thread, int(reg['msr'],16), eax, edx )
elif RegisterType.PORT == rtype:
port = int(reg['port'],16)
size = int(reg['size'],16)
_cs.io._write_port( port, reg_value, size )
elif RegisterType.IOBAR == rtype:
iobar = chipsec.hal.iobar( _cs )
iobar.write_IO_BAR_reg( reg['bar'], int(reg['offset'],16), reg_value )