def test_fsim_gate_family_raises():
with pytest.raises(ValueError, match='must be one of'):
_ = cirq_google.FSimGateFamily(gate_types_to_check=[cirq_google.SycamoreGate])
with pytest.raises(ValueError, match='Parameterized gate'):
_ = cirq_google.FSimGateFamily(gates_to_accept=[cirq.CZ ** sympy.Symbol('THETA')])
with pytest.raises(ValueError, match='must be either a type from or an instance of'):
_ = cirq_google.FSimGateFamily(gates_to_accept=[cirq.CNOT])
with pytest.raises(ValueError, match='must be either a type from or an instance of'):
_ = cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SycamoreGate])
with pytest.raises(ValueError, match='must be one of'):
_ = cirq_google.FSimGateFamily().convert(cirq.ISWAP, cirq_google.SycamoreGate)
def test_fsim_gate_family_convert_rejects():
# Non compatible, random 1/2/3 qubit gates.
for gate in [cirq.rx(np.pi / 2), cirq.CNOT, cirq.CCNOT]:
assert cirq_google.FSimGateFamily().convert(gate, cirq.PhasedFSimGate) is None
assert gate not in cirq_google.FSimGateFamily(gates_to_accept=[cirq.PhasedFSimGate])
# Custom gate with an overriden `_value_equality_values_cls_`.
assert UnequalSycGate() not in cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SYC])
assert UnequalSycGate(is_parameterized=True) not in cirq_google.FSimGateFamily(
gates_to_accept=[cirq_google.SYC], allow_symbols=True
)
# Partially paramaterized incompatible gate.
assert cirq.FSimGate(THETA, np.pi / 2) not in cirq_google.FSimGateFamily(
gates_to_accept=[cirq.PhasedISwapPowGate(exponent=0.5, phase_exponent=0.1), cirq.CZPowGate]
)
def test_grid_device_from_proto():
grid_qubits, spec = _create_device_spec_with_horizontal_couplings()
device = cirq_google.GridDevice.from_proto(spec)
assert len(device.metadata.qubit_set) == len(grid_qubits)
assert device.metadata.qubit_set == frozenset(grid_qubits)
assert all(
frozenset((cirq.GridQubit(row, 0), cirq.GridQubit(row, 1))) in device.metadata.qubit_pairs
for row in range(GRID_HEIGHT)
)
assert device.metadata.gateset == cirq.Gateset(
cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SYC]),
cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP]),
cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV]),
cirq_google.FSimGateFamily(gates_to_accept=[cirq.CZ]),
cirq.ops.phased_x_z_gate.PhasedXZGate,
cirq.ops.common_gates.XPowGate,
cirq.ops.common_gates.YPowGate,
cirq.ops.phased_x_gate.PhasedXPowGate,
cirq.GateFamily(
cirq.ops.common_gates.ZPowGate, tags_to_ignore=[cirq_google.PhysicalZTag()]
),
cirq.GateFamily(
cirq.ops.common_gates.ZPowGate, tags_to_accept=[cirq_google.PhysicalZTag()]
),
cirq_google.experimental.ops.coupler_pulse.CouplerPulse,
cirq.ops.measurement_gate.MeasurementGate,
cirq.ops.wait_gate.WaitGate,
)
assert tuple(device.metadata.compilation_target_gatesets) == (
cirq.CZTargetGateset(),
cirq_google.SycamoreTargetGateset(),
cirq.SqrtIswapTargetGateset(use_sqrt_iswap_inv=True),
)
base_duration = cirq.Duration(picos=1_000)
assert device.metadata.gate_durations == {
cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SYC]): base_duration * 0,
cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP]): base_duration * 1,
cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV]): base_duration * 2,
cirq_google.FSimGateFamily(gates_to_accept=[cirq.CZ]): base_duration * 3,
cirq.GateFamily(cirq.ops.phased_x_z_gate.PhasedXZGate): base_duration * 4,
cirq.GateFamily(cirq.ops.common_gates.XPowGate): base_duration * 4,
cirq.GateFamily(cirq.ops.common_gates.YPowGate): base_duration * 4,
cirq.GateFamily(cirq.ops.phased_x_gate.PhasedXPowGate): base_duration * 4,
cirq.GateFamily(
cirq.ops.common_gates.ZPowGate, tags_to_ignore=[cirq_google.PhysicalZTag()]
): base_duration
* 5,
cirq.GateFamily(
cirq.ops.common_gates.ZPowGate, tags_to_accept=[cirq_google.PhysicalZTag()]
): base_duration
* 6,
cirq.GateFamily(cirq_google.experimental.ops.coupler_pulse.CouplerPulse): base_duration * 7,
cirq.GateFamily(cirq.ops.measurement_gate.MeasurementGate): base_duration * 8,
cirq.GateFamily(cirq.ops.wait_gate.WaitGate): base_duration * 9,
}
def test_fsim_gate_family_eq():
eq = cirq.testing.EqualsTester()
eq.add_equality_group(
cirq_google.FSimGateFamily(),
cirq_google.FSimGateFamily(
gate_types_to_check=ALL_POSSIBLE_FSIM_GATES),
cirq_google.FSimGateFamily(
gate_types_to_check=ALL_POSSIBLE_FSIM_GATES[::-1]),
)
eq.add_equality_group(
cirq_google.FSimGateFamily(allow_symbols=True),
cirq_google.FSimGateFamily(gate_types_to_check=ALL_POSSIBLE_FSIM_GATES,
allow_symbols=True),
cirq_google.FSimGateFamily(
gate_types_to_check=ALL_POSSIBLE_FSIM_GATES[::-1],
allow_symbols=True),
)
eq.add_equality_group(
cirq_google.FSimGateFamily(
gates_to_accept=[
cirq_google.SYC,
cirq.SQRT_ISWAP,
cirq.SQRT_ISWAP,
cirq.CZPowGate,
cirq.PhasedISwapPowGate,
],
allow_symbols=True,
),
cirq_google.FSimGateFamily(
gates_to_accept=[
cirq.FSimGate(theta=np.pi / 2, phi=np.pi / 6),
cirq.SQRT_ISWAP,
cirq.CZPowGate,
cirq.CZPowGate,
cirq.PhasedISwapPowGate,
cirq.PhasedISwapPowGate,
],
gate_types_to_check=ALL_POSSIBLE_FSIM_GATES + [cirq.FSimGate],
allow_symbols=True,
),
cirq_google.FSimGateFamily(
gates_to_accept=[
cirq.FSimGate(theta=np.pi / 2, phi=np.pi / 6),
cirq.SQRT_ISWAP,
cirq.CZPowGate,
cirq.PhasedISwapPowGate,
],
gate_types_to_check=ALL_POSSIBLE_FSIM_GATES[::-1] +
[cirq.FSimGate],
allow_symbols=True,
),
)
def test_fsim_gate_family_convert_accept(gate, params, target_type):
# Test Parameterized gate conversion.
gate_family_allow_symbols = cirq_google.FSimGateFamily(allow_symbols=True)
assert isinstance(gate_family_allow_symbols.convert(gate, target_type), target_type)
# Test Non-Parameterized gate conversion.
resolved_gate = cirq.resolve_parameters(gate, params)
target_gate = cirq_google.FSimGateFamily().convert(resolved_gate, target_type)
assert isinstance(target_gate, target_type)
np.testing.assert_array_almost_equal(cirq.unitary(resolved_gate), cirq.unitary(target_gate))
# Test Parameterized gate accepted.
assert gate in cirq_google.FSimGateFamily(gates_to_accept=[target_type], allow_symbols=True)
assert gate in cirq_google.FSimGateFamily(gates_to_accept=[resolved_gate], allow_symbols=True)
# Test Non-Parameterized gate accepted.
assert resolved_gate in cirq_google.FSimGateFamily(gates_to_accept=[target_type])
assert resolved_gate in cirq_google.FSimGateFamily(gates_to_accept=[resolved_gate])
def _create_device_spec_with_horizontal_couplings():
# Qubit layout:
# x -- x
# x -- x
# x -- x
# x -- x
# x -- x
grid_qubits = [
cirq.GridQubit(i, j) for i in range(GRID_HEIGHT) for j in range(2)
]
spec = v2.device_pb2.DeviceSpecification()
spec.valid_qubits.extend([v2.qubit_to_proto_id(q) for q in grid_qubits])
qubit_pairs = []
grid_targets = spec.valid_targets.add()
grid_targets.name = '2_qubit_targets'
grid_targets.target_ordering = v2.device_pb2.TargetSet.SYMMETRIC
for row in range(int(GRID_HEIGHT / 2)):
qubit_pairs.append((cirq.GridQubit(row, 0), cirq.GridQubit(row, 1)))
for row in range(int(GRID_HEIGHT / 2), GRID_HEIGHT):
# Flip the qubit pair order for the second half of qubits
# to verify GridDevice properly handles pair symmetry.
qubit_pairs.append((cirq.GridQubit(row, 1), cirq.GridQubit(row, 0)))
for pair in qubit_pairs:
new_target = grid_targets.targets.add()
new_target.ids.extend([v2.qubit_to_proto_id(q) for q in pair])
gate_names = [
'syc',
'sqrt_iswap',
'sqrt_iswap_inv',
'cz',
'phased_xz',
'virtual_zpow',
'physical_zpow',
'coupler_pulse',
'meas',
'wait',
]
gate_durations = [(n, i * 1000) for i, n in enumerate(gate_names)]
for gate_name, duration in sorted(gate_durations):
gate = spec.valid_gates.add()
getattr(gate, gate_name).SetInParent()
gate.gate_duration_picos = duration
expected_gateset = cirq.Gateset(
cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SYC]),
cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP]),
cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV]),
cirq_google.FSimGateFamily(gates_to_accept=[cirq.CZ]),
cirq.ops.phased_x_z_gate.PhasedXZGate,
cirq.ops.common_gates.XPowGate,
cirq.ops.common_gates.YPowGate,
cirq.ops.phased_x_gate.PhasedXPowGate,
cirq.GateFamily(cirq.ops.common_gates.ZPowGate,
tags_to_ignore=[cirq_google.PhysicalZTag()]),
cirq.GateFamily(cirq.ops.common_gates.ZPowGate,
tags_to_accept=[cirq_google.PhysicalZTag()]),
cirq_google.experimental.ops.coupler_pulse.CouplerPulse,
cirq.ops.measurement_gate.MeasurementGate,
cirq.ops.wait_gate.WaitGate,
)
base_duration = cirq.Duration(picos=1_000)
expected_gate_durations = {
cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SYC]):
base_duration * 0,
cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP]):
base_duration * 1,
cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV]):
base_duration * 2,
cirq_google.FSimGateFamily(gates_to_accept=[cirq.CZ]):
base_duration * 3,
cirq.GateFamily(cirq.ops.phased_x_z_gate.PhasedXZGate):
base_duration * 4,
cirq.GateFamily(cirq.ops.common_gates.XPowGate):
base_duration * 4,
cirq.GateFamily(cirq.ops.common_gates.YPowGate):
base_duration * 4,
cirq.GateFamily(cirq.ops.phased_x_gate.PhasedXPowGate):
base_duration * 4,
cirq.GateFamily(cirq.ops.common_gates.ZPowGate,
tags_to_ignore=[cirq_google.PhysicalZTag()]):
base_duration * 5,
cirq.GateFamily(cirq.ops.common_gates.ZPowGate,
tags_to_accept=[cirq_google.PhysicalZTag()]):
base_duration * 6,
cirq.GateFamily(cirq_google.experimental.ops.coupler_pulse.CouplerPulse):
base_duration * 7,
cirq.GateFamily(cirq.ops.measurement_gate.MeasurementGate):
base_duration * 8,
cirq.GateFamily(cirq.ops.wait_gate.WaitGate):
base_duration * 9,
}
expected_target_gatesets = (
cirq.CZTargetGateset(),
cirq_google.SycamoreTargetGateset(),
cirq.SqrtIswapTargetGateset(use_sqrt_iswap_inv=True),
)
return (
_DeviceInfo(
grid_qubits,
qubit_pairs,
expected_gateset,
expected_gate_durations,
expected_target_gatesets,
),
spec,
)
gates_to_accept=[
cirq.FSimGate(theta=np.pi / 2, phi=np.pi / 6),
cirq.SQRT_ISWAP,
cirq.CZPowGate,
cirq.PhasedISwapPowGate,
],
gate_types_to_check=ALL_POSSIBLE_FSIM_GATES[::-1] + [cirq.FSimGate],
allow_symbols=True,
),
)
@pytest.mark.parametrize(
'gate_family',
[
cirq_google.FSimGateFamily(),
cirq_google.FSimGateFamily(allow_symbols=True),
cirq_google.FSimGateFamily(
gates_to_accept=[
cirq.FSimGate(theta=np.pi / 2, phi=np.pi / 6),
cirq.SQRT_ISWAP,
cirq.CZPowGate,
cirq.PhasedISwapPowGate,
],
gate_types_to_check=ALL_POSSIBLE_FSIM_GATES[::-1] + [cirq.FSimGate], # type:ignore
allow_symbols=True,
atol=1e-8,
),
],
)
def test_fsim_gate_family_repr(gate_family):
