def elaborate(self, platform):
m = Module()
clk_domains.load_clk(m)
for i in range(8):
with m.If(self.regs_en[i]):
m.d.full += self.registers[i].eq(self.registers[i] + 1)
return m
def elaborate(self, platform):
m = Module()
clk_domains.load_clk(m)
width_reg = Signal(16)
height_reg = Signal(16)
allowed_cycles_reg = Signal(24)
m.d.full += [
width_reg.eq(4096),
height_reg.eq(3072),
allowed_cycles_reg.eq(6666000),
]
m.d.comb += [
self.width.eq(width_reg),
self.height.eq(height_reg),
self.allowed_cycles.eq(allowed_cycles_reg),
]
return m
def elaborate(self, platform):
m = Module()
clk_domains.load_clk(m)
# register to hold data
reg = Signal(64)
reg_valid = Signal(1)
reg_tobe_invalid = Signal(1)
half_latched = Signal(1)
# wire o_busy
wire_obusy = Signal(1)
m.d.full += self.o_busy.eq(wire_obusy)
m.d.comb += [
reg_tobe_invalid.eq(0),
# ordinary this module is busy and will only go to un-busy
# if data is present in fifo and the register is empty.
wire_obusy.eq(1),
]
# valid input data, and there is no data in register or this data
# will not be needed next cycle, then register the data.
with m.If((self.valid_in == 1)
& ((reg_valid == 0) | (reg_tobe_invalid == 1))):
m.d.full += [
reg.eq(self.data_in),
reg_valid.eq(1),
]
m.d.comb += [
wire_obusy.eq(0),
]
# if there is valid data in the register but there is no valid data in the
# output, out the first half and set valid_out to 1.
with m.If((reg_valid == 1) & (self.valid_out == 0)
& (half_latched == 0)):
m.d.full += [
self.data_out.eq(reg[40:64]),
self.valid_out.eq(1),
half_latched.eq(1),
]
# if and output operation occurred [(self.i_busy==0) and (self.valid_out==1)]
# and there is valid data in register, then output the correct half.
with m.If((reg_valid == 1) & (self.i_busy == 0)
& (self.valid_out == 1)):
with m.If(half_latched == 1):
m.d.full += [
self.data_out.eq(reg[16:40]),
self.valid_out.eq(1),
half_latched.eq(0),
]
# in the last half, if there is no valid data ready the the
# reg_valid will turn to be 0.
m.d.comb += [
reg_tobe_invalid.eq(1),
]
with m.If(self.valid_in == 0):
m.d.full += [
reg_valid.eq(0),
]
with m.Else():
m.d.full += [
self.data_out.eq(reg[40:64]),
self.valid_out.eq(1),
half_latched.eq(1),
]
# if output operation occurred, and the reg_valid remains 0, then
# valid_out will turn to be 0.
with m.If((reg_valid == 0) & (self.i_busy == 0)
& (self.valid_out == 1)):
m.d.full += [
self.valid_out.eq(0),
]
return m
def elaborate(self, platform):
m = Module()
m.submodules.integration_3 = integration_3 = self.integration_3
m.submodules.fix_0xff = fix_0xff = self.fix_0xff
m.submodules.fix_0xff2 = fix_0xff2 = self.fix_0xff2
m.submodules.markers = markers = self.markers
m.submodules.auto_reset = auto_reset = self.auto_reset
clk_domains.load_clk(m)
# clk domain reset
m.d.comb += [
clk_domains.CORE.rst.eq((auto_reset.reset_out == 1)
| (clk_domains.FULL.rst == 1)),
]
# auto reset
m.d.comb += [
auto_reset.end_in.eq(self.end_out),
auto_reset.hs1_in.eq(self.valid_out),
auto_reset.hs2_in.eq(self.busy_in == 0),
]
if self.config['axi_lite_debug'] and self.config['support_axi_lite']:
# set debugging counters
trans_started = Signal(1)
m.d.sync += trans_started.eq(trans_started | self.valid_in)
debug_en = Signal(8)
m.d.sync += self.integration_3.integration_2.integration_1.core_axi_lite.debug_en.eq(
debug_en)
m.d.sync += debug_en[0].eq((trans_started == 1)
& (self.end_out == 0)
& (self.valid_in == 0))
m.d.sync += debug_en[1].eq((trans_started == 1)
& (self.end_out == 0)
& (self.valid_in == 1))
m.d.sync += debug_en[2].eq((trans_started == 1)
& (self.end_out == 0)
& (self.valid_out == 0))
m.d.sync += debug_en[3].eq((trans_started == 1)
& (self.end_out == 0)
& (self.valid_out == 1))
m.d.sync += debug_en[4].eq((trans_started == 1)
& (self.end_out == 0)
& (self.nready == 1))
m.d.sync += debug_en[5].eq((trans_started == 1)
& (self.end_out == 0)
& (self.nready == 0))
m.d.sync += debug_en[6].eq((trans_started == 1)
& (self.end_out == 0)
& (self.busy_in == 1))
m.d.sync += debug_en[7].eq((trans_started == 1)
& (self.end_out == 0)
& (self.busy_in == 0))
#in
m.d.comb += [
integration_3.pixels_in[0].eq(self.pixel_in1),
integration_3.pixels_in[1].eq(self.pixel_in2),
integration_3.valid_in.eq(self.valid_in),
integration_3.busy_in.eq(fix_0xff.o_busy),
]
#out
#int3 and fixer
m.d.comb += [
fix_0xff.data_in.eq(integration_3.data_out),
fix_0xff.valid_in.eq(integration_3.valid_out),
fix_0xff.end_in.eq(integration_3.end_out),
fix_0xff.i_busy.eq(fix_0xff2.o_busy),
]
#fixer1 and fixer2
m.d.comb += [
fix_0xff2.data_in.eq(fix_0xff.data_out),
fix_0xff2.valid_in.eq(fix_0xff.valid_out),
fix_0xff2.end_in.eq(fix_0xff.end_out),
fix_0xff2.i_busy.eq(markers.o_busy),
fix_0xff2.data_in_ctr.eq(fix_0xff.data_out_ctr),
]
#fixer2 and markers
m.d.comb += [
markers.data_in.eq(fix_0xff2.data_out),
markers.valid_in.eq(fix_0xff2.valid_out),
markers.force_end_in.eq(
integration_3.integration_2.integration_1.fend_out),
markers.end_in.eq(fix_0xff2.end_out),
markers.i_busy.eq(self.busy_in),
]
#out
m.d.comb += [
self.data_out.eq(markers.data_out),
self.valid_out.eq(markers.valid_out),
self.end_out.eq(markers.end_out),
self.nready.eq(integration_3.nready),
]
return m