def cmd_io_rw_extended(self, rw=0, fn=0, block=0, op=0, addr=0, count=0, data=None, blocksize=None, read_wait=None, could_abort=True):
"""
Send a CMD53, IO_RW_EXTENDED command
This is a data command and allows reading/writing to multiple address spaces with a single command.
Details in section 5.3 of SDIO spec (page 28)
args:
rw - 0: read, 1: write
fn - the function to access
block - whether we're doing a transfer in blocks or bytes
Block may or may not be supported, SMB bit in CCCR indicates so
op - 0: multi byte R/W to a fixed address, 1: to an incrementing address
address - not wider than 17-bits
count - depending on the mode it has different meanings
block == 1 ? 0: infinite (keep going until we sent an abort) 1: 1 block, 2: 2 blocks, etc.
block == 0 ? 0: 512 bytes , 1: 1 byte, 2: 2 bytes etc.
data - a list of data values (each not wider than 8-bits)
"""
cmd = sdio_utils.init_cmd(cmd_num=53)
cmd[39] = rw
cmd[38:36] = fn
cmd[35] = block
cmd[34] = op
cmd[33:17] = addr
cmd[16:8] = count
yield self.phy.acquire_cmd_lock()
yield self.phy.send_cmd(cmd)
response = yield self.get_cmd_response(cmd)
self.phy.release_cmd_lock()
if self.spi_mode:
pass
else:
# Inspect the response flags here
response_flags = BinaryValue(value=response[23:16].integer,bits=8,bigEndian=False)
if response_flags[7]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("IO_RW_DIRECT response flags: COM_CRC_ERROR")
if response_flags[6]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("IO_RW_DIRECT response flags: ILLEGAL_COMMAND")
if response_flags[3]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("IO_RW_DIRECT response flags: ERROR")
if response_flags[1]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("IO_RW_DIRECT response flags: FUNCTION_NUMBER (invalid function number %d)" % fn)
if response_flags[0]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("IO_RW_DIRECT response flags: OUT_OF_RANGE")
# TODO - this always responds 0 why?!
self.log.debug("IO_RW_EXTENDED response flags, IO_CURRENT_STATE: %d" %(response_flags[5:4].integer))
if block:
blocks = count
else:
blocks = 1
if rw:
assert(data != None)
for blockcount in range(0,blocks):
# Let's give a random number of bytes of clocks
random_pad_bytes = random.randint(1,4)
for _ in range(0,random_pad_bytes*8):
yield RisingEdge(self.clock)
if block:
self.log.debug("Writing block %d" %blockcount)
# Check if the block write has been aborted
if self.phy.data_write_aborted:
self.phy.data_write_aborted = False
self.log.info("Detected block write aborted after %d blocks" %(blockcount))
raise ReturnValue(0)
bytes_to_write = data[blockcount] if block else data
# Send data bytes on the data lines
crc_resp = yield self.phy.data_bus_write(bytes_to_write,could_abort=could_abort,final_block=blockcount+1==blocks)
# TODO check the CRC response and do something sensible with it
else:
blockdata = []
for blockcount in range(0,blocks):
if block:
assert(blocksize != None), "Called with block=1 but blocksize was not passed, please call with blocksize set"
bytes_to_read = blocksize if block else count
if block:
self.log.debug("Reading block %d" %blockcount)
data,status = yield self.phy.data_bus_read(bytes_to_read,could_abort=could_abort,final_block=blockcount+1==blocks)
if status == "aborted" or self.phy.data_read_aborted:
self.phy.data_read_aborted = False
# We were an aborted read, return what we have
raise ReturnValue(data)
if block:
blockdata.append(data)
# Wait a little bit before polling for the next data block
if self.spi_mode:
for _ in range(0,8):
yield RisingEdge(self.clock)
else:
# Wait a few cycles before polling the bus for the next block of data
yield FallingEdge(self.clock)
yield FallingEdge(self.clock)
# If we've been passed a read-wait period, do that
if read_wait:
self.phy.read_wait(True)
for x in range(read_wait):
yield FallingEdge(self.clock)
self.phy.read_wait(False)
if block:
raise ReturnValue(blockdata)
else:
raise ReturnValue(data)
raise ReturnValue(0)
def get_count(self): cnt = yield self._mst.rdxact(12) raise ReturnValue(cnt)
def read_reg(dut, addr):
dut.addr_i <= addr
yield RisingEdge(dut.clk_i)
raise ReturnValue(dut.data_o.value)
def wait_for(clk, cycles):
rising_edge = RisingEdge(clk)
for _ in range(cycles):
yield rising_edge
raise ReturnValue(3)
def read(self, addr):
value = yield self.wb.read(addr)
raise ReturnValue(value)
def read_from_i2c(self, i2c_id, read_length):
"""read_from_i2c_register
read from a register in the I2C device
Args:
i2c_id: Identification byte of the I2C (7-bit)
this value will be shifted left by 1
i2cwrite_register: data to write to that register (Array of bytes)
in order to read from an I2C device the user must write some
data to set up the device to read
read_length: Length of bytes to read from the device
Returns:
Array of bytes read from the I2C device
Raises:
NysaCommError: Error in communication
I2CError: Errors associated with the I2C protocol
"""
#self.debug = False
if self.debug: print "read_from_i2c: ENTERED"
#set up a write command
read_command = (i2c_id << 1) | 0x01
read_data = Array('B')
yield self.reset_i2c_core()
if self.debug:
print "\t\tGetting status before a read"
status = yield self.read_register(STATUS)
#self.print_status(status)
#set up interrupts
yield self.enable_interrupt(True)
#send the write command / i2c identification
yield self.write_register(TRANSMIT, (i2c_id << 1) | 0x01)
yield self.write_register(COMMAND, COMMAND_WRITE | COMMAND_START)
#wait 1 second for interrupt
if self.debug: print "Wait for interrupts..."
yield Timer(CLK_PERIOD * 1000)
d = self.is_interrupt_set(INT_TRANSFER_FINISHED)
if (d):
self.dut.log.info("Interrupt Detected")
yield self.acknowledge_interrupt(INT_TRANSFER_FINISHED)
#send the data
count = 0
if read_length > 1:
while count < read_length - 1:
status = yield self.get_status()
if self.debug:
print "\tReading %d" % count
yield self.write_register(COMMAND, COMMAND_READ)
#wait 1 second for interrupt
if self.debug: print "Wait for interrupts..."
yield Timer(CLK_PERIOD * 1000)
d = self.is_interrupt_set(INT_TRANSFER_FINISHED)
if (d):
self.dut.log.info("Interrupt Detected")
yield self.acknowledge_interrupt(INT_TRANSFER_FINISHED)
count = count + 1
#read the last peice of data
yield self.write_register(COMMAND, COMMAND_READ | COMMAND_NACK)
#wait 1 second for interrupt
if self.debug: print "Wait for interrupts..."
yield Timer(CLK_PERIOD * 1000)
d = self.is_interrupt_set(INT_TRANSFER_FINISHED)
if (d):
self.dut.log.info("Interrupt Detected")
yield self.acknowledge_interrupt(INT_TRANSFER_FINISHED)
yield self.write_register(COMMAND, COMMAND_STOP)
yield Timer(CLK_PERIOD * 1000)
#self.debug = False
raise ReturnValue(read_data)
def example():
yield Timer(10, 'ns')
raise ReturnValue(1)
def get_length(self):
value = yield self.read(self.IDX_LENGTH)
raise ReturnValue(value)
def get_prescaler(self):
value = yield self.read(self.IDX_PRESCALER)
raise ReturnValue(value)
def send_recv(self, data):
yield RisingEdge(self.clk)
yield self.send(data)
yield self.wait_irq()
read = yield self.recv()
raise ReturnValue(read.integer)
def recv(self):
value = yield self.read(self.IDX_READ)
raise ReturnValue(value)
def get_slave(self):
value = yield self.read(self.IDX_SLAVE)
raise ReturnValue(value)
def _read_data(self, address, len = 1):
data = yield self.axim.read(address << 2)
yield Timer(self.clk_period * 1)
raise ReturnValue(data)
def get_cmd_response(self,cmd,timeout=1000,timeout_possible=False):
"""
Await the response from the host to the command we sent,
and check a number of standard things in it.
"""
cmd_num = cmd[45:40].integer
if self.spi_mode:
response_type, response_length = sdio_utils.get_spi_response_type(cmd_num)
else:
response_type, response_length = sdio_utils.get_response_type(cmd_num)
response = yield self.phy.get_cmd_response_bits(cmd,timeout,timeout_possible)
if response is "timeout" and timeout_possible:
# Just return the timeout indication
raise ReturnValue(response)
if self.spi_mode:
# No CRC on command responses
if response_type in [4,7]:
r1_offset = 32
elif response_type == 5:
r1_offset = 8
else:
r1_offset = 0
self.log.debug("Getting R%d from CMD%d, data: %s",response_type,cmd_num,response.binstr)
# Check the R1 status fields
if response[r1_offset + 7]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("SPI command cmd%d response indicated parameter error (R1:%02x)" %(cmd_num,response.integer))
if response[r1_offset + 4]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("SPI command cmd%d response indicated function number error (R1:%02x)" %(cmd_num,response.integer))
if response[r1_offset + 3]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("SPI command cmd%d response indicated CRC error (R1:%02x)" %(cmd_num,response.integer))
if response[r1_offset + 2]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("SPI command cmd%d response indicated illegal instruction error (R1:%02x)" %(cmd_num,response.integer))
raise ReturnValue(response)
else:
# Do response checks
# Check the CRC7
crc7 = sdio_utils.crc7_gen(number=response[47:8].integer)
if crc7 != response[7:1].integer:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOProtocolError("Response CRC7 error: in response to cmd %d, expected CRC of %x got %x, response was 'b%s" %(cmd_num, crc7,
response[7:1].integer,
response.binstr))
response_cmd_num = response[45:40].integer
if response_type in [4]:
if response_cmd_num != 0x3f:
raise SDIOProtocolError("R4 reserved field [45:40] were not all set to 1, instead they were %x" %response_cmd_num)
elif response_cmd_num != cmd_num: # Other commands need to have their command number reflected here
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOProtocolError("Response cmd num error: in response to cmd %d, cmd field had %d" %(cmd_num,response_cmd_num))
if response_type in [1,1.5]:
# Could be a busy if 1.5, else it'll be type, let's look at the card status/
# We only care about a few bits, as specified in the SDIO spec 4.10.8 (page 23)
card_status = BinaryValue(value=response[39:8].integer,bits=32,bigEndian=False)
self.log.debug("R1 card status register: %x ('b%s)" %(card_status.integer, card_status.binstr))
if card_status[31]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("Card status register bit 31, OUT_OF_RANGE, set in response to cmd%d" %(cmd_num))
if card_status[23]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("Card status register bit 23, COM_CRC_ERROR, set in response to cmd%d" %(cmd_num))
if card_status[22]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("Card status register bit 22, ILLEGAL_COMMAND (not legal for current state), set in response to cmd%d" %(cmd_num))
if card_status[19]:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("Card status register bit 19, ERROR (general or unknown error), set in response to cmd%d" %(cmd_num))
if card_status[12:9].integer != 0xf:
for _ in range(0,4): yield FallingEdge(self.clock)
raise SDIOResponseError("Card status register CURRENT_STATE != 0xf, which it should be for an SDIO card")
raise ReturnValue(response)
def get_interrupt_enable(self):
d = yield self.read_register(INTERRUPT_EN)
raise ReturnValue(d)
def get_status(self):
value = yield self.read(self.IDX_STATUS)
raise ReturnValue(value)
def is_interrupt_set(self, interrupt):
d = yield self.read_register(INTERRUPT)
if (d & (1 << interrupt) > 0):
raise ReturnValue(True)
raise ReturnValue(False)
def read(self, address, sync=True):
"""Issue a request to the bus and block until this
comes back. Simulation time still progresses
but syntactically it blocks.
Args:
address (int): The address to read from.
sync (bool, optional): Wait for rising edge on clock initially.
Defaults to True.
Returns:
BinaryValue: The read data value.
Raises:
:any:`TestError`: If master is write-only.
"""
if not self._can_read:
self.log.error("Cannot read - have no read signal")
raise TestError("Attempt to read on a write-only AvalonMaster")
yield self._acquire_lock()
# Apply values for next clock edge
if sync:
yield RisingEdge(self.clock)
self.bus.address <= address
self.bus.read <= 1
if hasattr(self.bus, "byteenable"):
self.bus.byteenable <= int("1" * len(self.bus.byteenable), 2)
if hasattr(self.bus, "cs"):
self.bus.cs <= 1
# Wait for waitrequest to be low
if hasattr(self.bus, "waitrequest"):
yield self._wait_for_nsignal(self.bus.waitrequest)
yield RisingEdge(self.clock)
# Deassert read
self.bus.read <= 0
if hasattr(self.bus, "byteenable"):
self.bus.byteenable <= 0
if hasattr(self.bus, "cs"):
self.bus.cs <= 0
v = self.bus.address.value
v.binstr = "x" * len(self.bus.address)
self.bus.address <= v
if hasattr(self.bus, "readdatavalid"):
while True:
yield ReadOnly()
if int(self.bus.readdatavalid):
break
yield RisingEdge(self.clock)
else:
# Assume readLatency = 1 if no readdatavalid
# FIXME need to configure this,
# should take a dictionary of Avalon properties.
yield ReadOnly()
# Get the data
data = self.bus.readdata.value
self._release_lock()
raise ReturnValue(data)
def immediate_value():
raise ReturnValue(42)
yield
def read(address):
master.log.debug("External source: reading address 0x%08X" % address)
value = yield master.read(address)
master.log.debug("Reading complete: got value 0x%08x" % value)
raise ReturnValue(value)
def some_coro():
yield Timer(1)
raise ReturnValue(retval)
def yield_to_readwrite(dut):
yield RisingEdge(dut.clk)
dut._log.info("Returning from yield_to_readwrite")
raise ReturnValue(2)
def pending(self, ep):
if EndpointType.epdir(ep) == EndpointType.IN:
val = yield self.read(self.csrs['usb_epin_status'])
else:
val = yield self.read(self.csrs['usb_epout_status'])
raise ReturnValue(val & 1)
def read_register(self, dest, src, word_width, regaddr):
"""
Read a value from a specified register and return the read value to
the user.
Args:
dest: DI address of the target module.
src: DI address of the sending module.
word_width: choose between 16, 32, 64 and 128 bit register
access.
regaddr: address of the register the value is to be read
from.
Returns:
Value read from the register
"""
tx_packet = DiPacket()
rx_packet = DiPacket()
try:
if word_width == 16:
type_sub = DiPacket.TYPE_SUB.REQ_READ_REG_16.value
exp_type_sub = \
DiPacket.TYPE_SUB.RESP_READ_REG_SUCCESS_16.value
elif word_width == 32:
type_sub = DiPacket.TYPE_SUB.REQ_READ_REG_32.value
exp_type_sub = \
DiPacket.TYPE_SUB.RESP_READ_REG_SUCCESS_32.value
elif word_width == 64:
type_sub = DiPacket.TYPE_SUB.REQ_READ_REG_64.value
exp_type_sub = \
DiPacket.TYPE_SUB.RESP_READ_REG_SUCCESS_64.value
elif word_width == 128:
type_sub = DiPacket.TYPE_SUB.REQ_READ_REG_128.value
exp_type_sub = \
DiPacket.TYPE_SUB.RESP_READ_REG_SUCCESS_128.value
else:
raise RegAccessFailedException("An invalid register width " +
"parameter was chosen!")
tx_packet.set_contents(dest=dest,
src=src,
type=DiPacket.TYPE.REG.value,
type_sub=type_sub,
payload=[regaddr])
yield self.writer.send_packet(tx_packet)
# Get response
rx_packet = yield self.reader.receive_packet(set_ready=True)
# Check response
if rx_packet.dest != src:
self.dut._log.info(str(src))
self.dut._log.info(str(rx_packet))
raise RegAccessFailedException("Expected destination to be "
"0x%x, got 0x%x" %
(src, rx_packet.dest))
if rx_packet.src != dest:
raise RegAccessFailedException("Expected source to be 0x%x, "
"got 0x%x" %
(dest, rx_packet.src))
if rx_packet.type != DiPacket.TYPE.REG.value:
raise RegAccessFailedException(
"Expected type to be %s, got %s" %
(DiPacket.TYPE.REG.name, DiPacket.TYPE(
rx_packet.type).name))
if rx_packet.type_sub == DiPacket.TYPE_SUB.RESP_READ_REG_ERROR.value:
raise RegAccessFailedException(
"Module returned RESP_READ_REG_ERROR")
if rx_packet.type_sub != exp_type_sub:
raise RegAccessFailedException(
"Expected subtype to be %s, got %s" %
(DiPacket.TYPE_SUB(exp_type_sub).name,
DiPacket.TYPE_SUB(rx_packet.type_sub).name))
# Extract register value from response
rx_value = 0
nr_words = int((word_width / 16))
if len(rx_packet.payload) != nr_words:
raise RegAccessFailedException(
"Expected %d payload words in "
"response, got %d." % (nr_words, len(rx_packet.payload)))
for w in range(0, nr_words):
shift_bit = (nr_words - w - 1) * 16
rx_value |= rx_packet.payload[w] << shift_bit
self.dut._log.debug(
"Successfully read %d bit register 0x%04x from "
"module at DI address 0x%04x. Got value 0x%x." %
(word_width, regaddr, dest, rx_value))
except RegAccessFailedException as reg_acc_error:
self.dut._log.info(reg_acc_error.message)
rx_value = None
raise ReturnValue(rx_value)
def _wait(self):
trigger = self._type(self.signal)
for _ in range(self.num_cycles):
yield trigger
raise ReturnValue(self)
def write_register(self,
dest,
src,
word_width,
regaddr,
value,
fatal_errors=True):
"""
Write a new value into a register specified by the user and read
the response to tell the user if the write process was successful
Args:
dest: id of the target module.
src: id of the sending module.
word_width: choose between 16, 32, 64 and 128 bit register
access.
regaddr: address of the register the new value will be
written to.
value: value to write to the register
"""
tx_packet = DiPacket()
rx_packet = DiPacket()
try:
if word_width == 16:
type_sub = DiPacket.TYPE_SUB.REQ_WRITE_REG_16.value
words = 1
elif word_width == 32:
type_sub = DiPacket.TYPE_SUB.REQ_WRITE_REG_32.value
words = 2
elif word_width == 64:
type_sub = DiPacket.TYPE_SUB.REQ_WRITE_REG_64.value
words = 3
elif word_width == 128:
type_sub = DiPacket.TYPE_SUB.REQ_WRITE_REG_128.value
words = 4
else:
raise RegAccessFailedException("An invalid register width "
"parameter was chosen!")
# Assemble payload of REG debug packet
payload = [regaddr]
for w in range(0, words):
payload.append((value >> ((words - 1 - w) * 16)) & 0xFFFF)
tx_packet.set_contents(dest=dest,
src=src,
type=DiPacket.TYPE.REG.value,
type_sub=type_sub,
payload=payload)
yield self.writer.send_packet(tx_packet)
rx_packet = yield self.reader.receive_packet(set_ready=True)
if not rx_packet:
raise RegAccessFailedException("No response packet received.")
if rx_packet.type_sub == DiPacket.TYPE_SUB.RESP_WRITE_REG_ERROR.value:
raise RegAccessFailedException(
"Register write failed, DUT returned RESP_WRITE_REG_ERROR "
"when writing 0x%x to register 0x%x of module 0x%x." %
(value, regaddr, dest))
if rx_packet.type_sub != DiPacket.TYPE_SUB.RESP_WRITE_REG_SUCCESS.value:
raise RegAccessFailedException(
"Expected subtype to be %s, got %s" %
(DiPacket.TYPE_SUB.RESP_WRITE_REG_SUCCESS.name,
DiPacket.TYPE_SUB(rx_packet.type_sub).name))
self.dut._log.debug("Successfully wrote %d bit register 0x%04x of "
"module at DI address 0x%04x." %
(word_width, regaddr, dest))
success = True
except RegAccessFailedException as reg_acc_error:
if fatal_errors:
raise TestFailure(reg_acc_error.message)
else:
self.dut._log.info(reg_acc_error.message)
success = False
raise ReturnValue(success)
def write(self,
address,
value,
byte_enable=0xf,
address_latency=0,
data_latency=0,
sync=True):
"""
Write a value to an address.
Args:
address (int): The address to write to
value (int): The data value to write
byte_enable (int, optional): Which bytes in value to actually write.
Default is to write all bytes.
address_latency (int, optional): Delay before setting the address (in clock cycles).
Default is no delay.
data_latency (int, optional): Delay before setting the data value (in clock cycles).
Default is no delay.
sync (bool, optional): Wait for rising edge on clock initially.
Defaults to True.
Returns:
BinaryValue: The write response value
Raises:
AXIProtocolError: If write response from AXI is not ``OKAY``
"""
if sync:
yield RisingEdge(self.clock)
c_addr = cocotb.fork(
self._send_write_address(address, delay=address_latency))
c_data = cocotb.fork(
self._send_write_data(value,
byte_enable=byte_enable,
delay=data_latency))
if c_addr:
yield c_addr.join()
if c_data:
yield c_data.join()
# Wait for the response
while True:
yield ReadOnly()
if self.bus.BVALID.value and self.bus.BREADY.value:
result = self.bus.BRESP.value
self.log.debug("Writing to address 0x%08x with 0x%08x" %
(address, value))
break
yield RisingEdge(self.clock)
yield RisingEdge(self.clock)
if int(result):
raise AXIProtocolError(
"Write to address 0x%08x failed with BRESP: %d" %
(address, int(result)))
raise ReturnValue(result)
def wrapper():
ext = cocotb.scheduler.run_in_executor(self._func, *args, **kwargs)
yield ext.event.wait()
ret = ext.result # raises if there was an exception
raise ReturnValue(ret)
def _delay(self, duration, units='sec'):
# Wrap Timer() in coroutine to allow forking.
yield Timer(duration, units=units)
raise ReturnValue(duration) # change to return dur for Python3
def function(x):
yield Timer(1)
raise ReturnValue(x)