class ChisNesPadTest(object):
"""
"""
LOGLEVEL = logging.INFO
PERIOD = (20, "ns")
SUPER_NES_LEN = 16
NES_LEN = 8
def __init__(self, dut, reg_init_value=0xcafe, reg_len=16):
if sys.version_info[0] < 3:
raise Exception("Must be using Python 3")
self._dut = dut
self._dut._log.setLevel(self.LOGLEVEL)
self.log = SimLog("ChisNesPad.{}".format(self.__class__.__name__))
self.log.setLevel(self.LOGLEVEL)
self.reg_init_value = reg_init_value
self._reg = reg_init_value
self._reg_count = reg_len
self._reg_len = reg_len
self.clock = Clock(self._dut.clock, self.PERIOD[0], self.PERIOD[1])
self._clock_thread = cocotb.fork(self.clock.start())
self._register_thread = cocotb.fork(self._register())
@cocotb.coroutine
def reset(self):
short_per = Timer(100, units="ns")
self._dut.reset <= 1
self._dut.io_sdata <= 0
self._dut.io_data_ready <= 0
yield short_per
self._dut.reset <= 1
yield short_per
self._dut.reset <= 0
yield short_per
@cocotb.coroutine
def _register(self):
while True:
try:
dlatch = int(self._dut.io_dlatch)
except ValueError:
dlatch = 1
if dlatch != 0:
yield FallingEdge(self._dut.io_dlatch)
self._reg = self.reg_init_value
self._reg_count = self._reg_len
sdata_bit = (self.reg_init_value &
(0x1 <<
(self._reg_len - 1))) >> (self._reg_len - 1)
self._dut.io_sdata <= sdata_bit
else:
sdata_bit = self._reg & (0x1 << (self._reg_len - 1))
self._dut.io_sdata <= (sdata_bit != 0)
if self._reg_count != 0:
self._reg = (self._reg << 1)
yield [
RisingEdge(self._dut.io_dclock),
RisingEdge(self._dut.io_dlatch)
]
class WbGpio(object):
""" test class for Spi2KszTest
"""
LOGLEVEL = logging.INFO
# clock frequency is 50Mhz
PERIOD = (20, "ns")
STATUSADDR = 0
DIRADDR = 1
READADDR = 2
WRITEADDR = 3
def __init__(self, dut):
if sys.version_info[0] < 3:
raise Exception("Must be using Python 3")
self._dut = dut
self.log = SimLog("wbGpio.{}".format(self.__class__.__name__))
self._dut._log.setLevel(self.LOGLEVEL)
self.log.setLevel(self.LOGLEVEL)
self.clock = Clock(self._dut.clock, self.PERIOD[0], self.PERIOD[1])
self._clock_thread = cocotb.fork(self.clock.start())
self.wbs = WishboneMaster(
dut,
"io_wbs",
dut.clock,
width=16, # size of data bus
timeout=10, # in clock cycle number
signals_dict={
"cyc": "cyc_i",
"stb": "stb_i",
"we": "we_i",
"adr": "adr_i",
"datwr": "dat_i",
"datrd": "dat_o",
"ack": "ack_o"
})
def get_dut_version_str(self):
return "{}".format(self._dut.version)
@cocotb.coroutine
def reset(self):
self._dut.reset <= 1
short_per = Timer(100, units="ns")
yield short_per
self._dut.reset <= 1
yield short_per
self._dut.reset <= 0
yield short_per
class SPIModule(Driver, Monitor):
""" test class for SPI """
def __init__(self, config, signals, clk, *, clk_freq=None):
self.log = SimLog("cocotbext.spi.{}".format(self.__class__.__name__))
self.log.setLevel(config.loglevel)
self.config = config
self.clk = clk
if clk_freq is None:
clk_freq = 1 / get_time_from_sim_steps(clk.period, "sec")
self.miso = signals.miso
self.mosi = signals.mosi
self.cs = signals.cs
self.sclk = signals.sclk
# chip select Edging
if self.config.csphase:
self.csBeginEdge = RisingEdge(self.cs)
self.csEndEdge = FallingEdge(self.cs)
else:
self.csBeginEdge = FallingEdge(self.cs)
self.csEndEdge = RisingEdge(self.cs)
# sclk edging
# CPOL | leading edge | trailing edge
# ------|--------------|--------------
# false | rising | falling
# true | falling | rising
if self.config.cpol:
self.sclkLeadEdge = FallingEdge(self.sclk)
self.sclkTrailEdge = RisingEdge(self.sclk)
else:
self.sclkLeadEdge = RisingEdge(self.sclk)
self.sclkTrailEdge = FallingEdge(self.sclk)
# CPHA | data change | data read
# ------|----------------|--------------
# false | trailling edge | leading edge
# true | leading edge | trailing edge
if self.config.cpha:
self.dataChangEdge = self.sclkLeadEdge
self.dataReadEdge = self.sclkTrailEdge
else:
self.dataChangEdge = self.sclkTrailEdge
self.dataReadEdge = self.sclkLeadEdge
Driver.__init__(self)
Monitor.__init__(self)
def sig_init(self):
self.mosi <= 0
self.sclk <= 0
self.cs <= int(not self.config.csphase)
def set_cs(self, enable):
if enable:
self.cs <= int(self.config.csphase)
else:
self.cs <= int(not self.config.csphase)
@coroutine
def read(self, address, sync=True):
""" Reading value on SPI """
raise Exception("TODO: read a value on SPI with read()")
@coroutine
def write(self, address, values_list):
""" Writing value on SPI"""
raise Exception("TODO: write values on SPI with write()")
@coroutine
def _driver_send(self, transaction, sync=True, **kwargs):
short_per = Timer(100, units="ns")
sclk_per = Timer(self.config.baudrate[0],
units=self.config.baudrate[1])
#initial state
self.sclk <= 0
yield sclk_per
for i in range(8):
self.sclk <= 1
self.mosi <= (transaction >> (7 - i)) & 0x01
yield sclk_per
self.sclk <= 0
yield sclk_per
@coroutine
def _monitor_recv(self):
while True:
miso = ""
mosi = ""
yield self.csBeginEdge
while int(self.cs) == int(self.config.csphase):
trig = yield [self.dataReadEdge, self.csEndEdge]
if trig == self.dataReadEdge:
miso = miso + self.miso.value.binstr
mosi = mosi + self.mosi.value.binstr
values_recv = {"miso": miso, "mosi": mosi}
self._recv(values_recv)
class Eim2Wishbone(object):
"""
"""
LOGLEVEL = logging.INFO
# clock frequency is 50Mhz
PERIOD = (20, "ns")
STATUSADDR = 0
DIRADDR = 1
READADDR = 2
WRITEADDR = 3
def __init__(self, dut):
if sys.version_info[0] < 3:
raise Exception("Must be using Python 3")
self._dut = dut
self._mem = {}
self.log = SimLog("Eim2Wishbone.{}".format(self.__class__.__name__))
self._dut._log.setLevel(self.LOGLEVEL)
self.log.setLevel(self.LOGLEVEL)
self.clock = Clock(self._dut.clock, self.PERIOD[0], self.PERIOD[1])
self._clock_thread = cocotb.fork(self.clock.start())
self.log.info("instanciate slave")
self.wbm = WishboneSlave(
dut,
"io_wbm",
dut.clock,
width=16, # size of data bus
waitreplygen=repeat(3),
datgen=self._memory(),
signals_dict={
"cyc": "cyc_o",
"stb": "stb_o",
"we": "we_o",
"adr": "adr_o",
"datwr": "dat_o",
"datrd": "dat_i",
"ack": "ack_i"
})
self.eim = EIMMaster(dut, "io_eim", dut.clock, width=16)
# manage accesses like a memory
def _memory(self):
mem = {
0: 0xcafe,
1: 0xdeca,
2: 0xcaca,
3: 0xbebe,
}
while True:
adr = self.wbm.bus.adr.value.integer
self.log.info(f"adr : {adr}")
yield mem.get(adr, 0xffff)
def log_transaction(self, transaction):
self.log.info("callbacks {}".format(transaction))
@cocotb.coroutine
def reset(self):
self._dut.reset <= 1
short_per = Timer(100, units="ns")
yield short_per
self._dut.reset <= 1
yield short_per
self._dut.reset <= 0
yield short_per