def genWrite(self):
idOffset = randBits(2)
writeCmd = Transaction()
writeCmd.addr = self.genRandomAddress()
if random.random() < 0.1: # Random assertion of decoding error
writeCmd.addr = 1 << 12
writeCmd.hid = self.hid * 4 + idOffset #Each master can use 4 id
writeCmd.region = randBits(4)
writeCmd.len = randBits(4)
writeCmd.size = randBits(3)
writeCmd.burst = randBits(2)
writeCmd.lock = randBits(1)
writeCmd.cache = randBits(4)
writeCmd.qos = randBits(4)
writeCmd.prot = randBits(3)
self.writeCmdQueue.put(writeCmd)
writeCmd.linkedDatas = []
for i in range(writeCmd.len + 1):
writeData = Transaction()
writeData.data = randBits(32)
writeData.strb = randBits(4)
writeData.last = 1 if i == writeCmd.len else 0
self.writeDataQueue.put(writeData)
writeCmd.linkedDatas.append(writeData)
self.idToWrites[writeCmd.hid].append(writeCmd)
def read(self, address, rsp):
ar = Transaction()
ar.addr = address
ar.prot = 0
self.arQueue.put(ar)
while True:
yield RisingEdge(self.clk)
if self.axiLite.r.valid == True and self.axiLite.r.ready == True:
rsp[0] = int(self.axiLite.r.payload.data)
break
def write(self, address, data):
aw = Transaction()
aw.addr = address
aw.prot = 0
self.awQueue.put(aw)
w = Transaction()
w.data = data
w.strb = 0xF
self.wQueue.put(w)
while True:
yield RisingEdge(self.clk)
if self.axiLite.b.valid == True and self.axiLite.b.ready == True:
break
def genReadCmd(self):
if self.closeIt:
return None
if not self.readCmdIdleRand.get():
return None
idOffset = randBits(2)
trans = Transaction()
trans.addr = self.genRandomReadAddress()
trans.hid = self.idBase*4 + idOffset #Each master can use 4 id
trans.region = randBits(4)
trans.len = randBits(4)
trans.size = randBits(3)
trans.burst = randBits(2)
trans.lock = randBits(1)
trans.cache = randBits(4)
trans.qos = randBits(4)
trans.prot = randBits(3)
return trans
def genReadCmd(self):
if self.closeIt:
return None
if not self.readCmdIdleRand.get():
return None
idOffset = randBits(2)
trans = Transaction()
trans.addr = self.genRandomReadAddress()
trans.hid = self.idBase * 4 + idOffset #Each master can use 4 id
trans.region = randBits(4)
trans.len = randBits(4)
trans.size = randBits(3)
trans.burst = randBits(2)
trans.lock = randBits(1)
trans.cache = randBits(4)
trans.qos = randBits(4)
trans.prot = randBits(3)
return trans
def genWrite(self):
idOffset = randBits(2)
writeCmd = Transaction()
writeCmd.addr = self.genRandomWriteAddress()
writeCmd.hid = self.idBase + idOffset #Each master can use 4 id
writeCmd.region = randBits(4)
writeCmd.len = randBits(4)
writeCmd.size = randBits(3)
writeCmd.burst = randBits(2)
writeCmd.lock = randBits(1)
writeCmd.cache = randBits(4)
writeCmd.qos = randBits(4)
writeCmd.prot = randBits(3)
self.writeCmdQueue.put(writeCmd)
for i in xrange(writeCmd.len + 1):
writeData = Transaction()
writeData.data = writeCmd.addr + i
writeData.strb = (writeCmd.addr + i) & 0xF
writeData.last = 1 if i == writeCmd.len else 0
self.writeDataQueue.put(writeData)
def genWrite(self):
idOffset = randBits(2)
writeCmd = Transaction()
writeCmd.addr = self.genRandomWriteAddress()
writeCmd.hid = self.idBase + idOffset #Each master can use 4 id
writeCmd.region = randBits(4)
writeCmd.len = randBits(4)
writeCmd.size = randBits(3)
writeCmd.burst = randBits(2)
writeCmd.lock = randBits(1)
writeCmd.cache = randBits(4)
writeCmd.qos = randBits(4)
writeCmd.prot = randBits(3)
self.writeCmdQueue.put(writeCmd)
for i in range(writeCmd.len + 1):
writeData = Transaction()
writeData.data = writeCmd.addr + i
writeData.strb = (writeCmd.addr + i) & 0xF
writeData.last = 1 if i == writeCmd.len else 0
self.writeDataQueue.put(writeData)
def genReadCmd(self):
if self.doFinish:
return None
if not self.readCmdIdleRand.get():
return None
idOffset = randBits(2)
trans = Transaction()
trans.addr = self.genRandomAddress()
if random.random() < 0.1: # Random assertion of decoding error
trans.addr = 1 << 12
trans.hid = self.hid * 4 + idOffset #Each master can use 4 id
trans.region = randBits(4)
trans.len = randBits(4)
trans.size = randBits(3)
trans.burst = randBits(2)
trans.lock = randBits(1)
trans.cache = randBits(4)
trans.qos = randBits(4)
trans.prot = randBits(3)
trans.progress = 0
self.readMonitorQueues[idOffset].put(trans)
# print("Master START %d %x" % (trans.hid, trans.addr))
return trans
def genNewCmd(self):
cmd = Transaction()
cmd.hid = randBits(self.idWidth) # Each master can use 4 id
cmd.region = randBits(4)
cmd.len = randBits(4)
cmd.size = random.randint(0, self.maxDataBytes)
cmd.burst = random.randint(0, 2)
if cmd.burst == 2:
cmd.len = random.choice([2, 4, 8, 16]) - 1
else:
cmd.len = randBits(4) + (16 if random.random() < 0.1 else
0) + (32 if random.random() < 0.02 else 0)
cmd.lock = randBits(1)
cmd.cache = randBits(4)
cmd.qos = randBits(4)
cmd.prot = randBits(3)
byteCount = (1 << cmd.size) * (cmd.len + 1)
while (True):
cmd.addr = self.genRandomeAddress() & ~((1 << cmd.size) - 1)
if cmd.burst == 1:
if cmd.addr + byteCount >= (1 << self.addressWidth):
continue
if cmd.burst == 0:
start = cmd.addr
end = start + cmd.size
if cmd.burst == 1:
start = cmd.addr
end = start + byteCount
if cmd.burst == 2:
start = cmd.addr & ~(byteCount - 1)
end = start + byteCount
if self.isAddressRangeBusy(start, end):
continue
break
if self.readWriteRand.get():
cmd.write = 1
beatAddr = cmd.addr
for i in range(cmd.len + 1):
dataTrans = Transaction()
dataTrans.data = randBits(self.dataWidth)
dataTrans.strb = randBits(self.maxDataBytes)
dataTrans.last = 1 if cmd.len == i else 0
self.writeTasks.put(dataTrans)
for s in range(self.maxDataBytes):
if (dataTrans.strb >> s) & 1 == 1:
self.ram[(beatAddr & ~(self.maxDataBytes - 1)) +
s] = (dataTrans.data >> (s * 8)) & 0xFF
beatAddr = Axi4AddrIncr(beatAddr, cmd.burst, cmd.len, cmd.size)
writeRsp = Transaction()
writeRsp.resp = 0
writeRsp.hid = cmd.hid
self.reservedAddresses[writeRsp] = [start, end]
self.writeRspScoreboard.refPush(writeRsp, writeRsp.hid)
else:
cmd.write = 0
beatAddr = cmd.addr
for s in range(cmd.len + 1):
readRsp = Transaction()
addrBase = beatAddr & ~(self.maxDataBytes - 1)
readRsp.data = 0
for i in range(self.maxDataBytes):
readRsp.data |= self.ram[addrBase + i] << (i * 8)
readRsp.resp = 0
readRsp.last = 1 if cmd.len == s else 0
readRsp.hid = cmd.hid
if readRsp.last == 1:
self.reservedAddresses[readRsp] = [start, end]
self.readRspScoreboard.refPush(readRsp, readRsp.hid)
beatAddr = Axi4AddrIncr(beatAddr, cmd.burst, cmd.len, cmd.size)
self.cmdTasks.put(cmd)