def SlaveThread(scl, sda, clk, baudPeriod): global crapyConflictCounter global normalConflictCounter global normalTransactionCounter log.debug("x") IDLE = 0 START = 1 DATA = 2 state = IDLE dataState = 0 scl.write(True) sda.write(True) sclLast = True sdaLast = True while True: yield RisingEdge(clk) sclValue = scl.read() sdaValue = sda.read() sclRising = sclValue and not sclLast sclFalling = not sclValue and sclLast sdaRising = sdaValue and not sdaLast sdaFalling = not sdaValue and sdaLast sclLast = sclValue sdaLast = sdaValue if state == IDLE: if sdaFalling and sclValue: state = START elif state == START: if sclFalling: state = DATA dataState = 0 address = 0 elif state == DATA: if sclRising: if dataState < 8: address |= sdaValue << (7 - dataState) elif sclFalling: dataState += 1 if dataState >= 8 and dataState < 16: if random.random() < 0.2: #Clock stretching scl.write(False) yield Timer(randInt(baudPeriod / 10, baudPeriod * 10)) sda.write((cmdToData[address] >> (15 - dataState)) & 1) yield Timer(baudPeriod / 4) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) sclLast = False else: sda.write((cmdToData[address] >> (15 - dataState)) & 1) elif (dataState == 6 and random.random() < 0.2): scl.write(False) if random.random() < 0.2: # Clock stretching yield Timer(randInt(baudPeriod / 10, baudPeriod * 10)) yield Timer(baudPeriod / 2) sda.write(False) yield Timer(baudPeriod / 2) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) yield Timer(baudPeriod) if random.random() < 0.5: #Normal conflict normalConflictCounter += 1 for i in range(4): rand = randBool() scl.write(False) yield Timer(baudPeriod / 2) sda.write(rand) yield Timer(baudPeriod / 2) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) yield Timer(baudPeriod) assert sda.read() == rand scl.write(False) yield Timer(baudPeriod / 2) sda.write(False) yield Timer(baudPeriod / 2) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) yield Timer(baudPeriod) sda.write(True) else: #crapy conflict wihtout STOP crapyConflictCounter += 1 scl.write(False) yield Timer(baudPeriod / 2) sda.write(True) yield Timer(baudPeriod / 2) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) yield Timer(baudPeriod) state = IDLE continue else: if random.random() < 0.2: #Clock stretching scl.write(False) yield Timer(randInt(baudPeriod / 10, baudPeriod * 10)) sda.write(True) yield Timer(baudPeriod / 4) scl.write(True) sclLast = False else: sda.write(True) elif sclValue: if sdaRising: state = 0 if sdaFalling: state = 1 pass
def run(self): global crapyConflictCounter global normalConflictCounter global normalTransactionCounter yield Timer(self.baudPeriod * 10) while crapyConflictCounter < 2 or normalConflictCounter < 3 or normalTransactionCounter < 40: while True: colision = False cmd = Transaction() cmd.mode = 0 cmd.data = randBool() self.cmdQueue.append(cmd) address = randBits(8) | 2 for bitId in range(8): cmd = Transaction() cmd.mode = 1 cmd.data = (address >> (7 - bitId)) & 1 self.cmdQueue.append(cmd) yield clockedWaitTrue(self.clk, self.rsp.valid) if self.rsp.payload.data != cmd.data: assert bitId == 6 colision = True cmd = Transaction() cmd.mode = 3 #DROP cmd.data = randBool() self.cmdQueue.append(cmd) break if colision: continue for bitId in range(8): cmd = Transaction() cmd.mode = 1 cmd.data = True self.cmdQueue.append(cmd) yield clockedWaitTrue(self.clk, self.rsp.valid) assert self.rsp.payload.data == ((cmdToData[address] >> (7 - bitId)) & 1) if random.random() < 0.75: cmd = Transaction() cmd.mode = 2 cmd.data = randBool() self.cmdQueue.append(cmd) if random.random() < 0.75: #no other master frame if random.random() < 0.5: # With inter frame delay yield Timer(randInt(0, self.baudPeriod * 20)) else: @coroutine def anotherFrameEmiter(): yield self.softMaster.sendStart() for i in range(5): yield self.softMaster.sendBit(randBool()) yield self.softMaster.sendStop() yield Timer( randInt(self.baudPeriod * 4, self.baudPeriod * 10)) fork(anotherFrameEmiter()) yield Timer( randInt(self.baudPeriod * 1, self.baudPeriod * 14)) normalTransactionCounter += 1 break while self.cmdQueue: yield Timer(self.baudPeriod * 10)
def anotherFrameEmiter(): yield self.softMaster.sendStart() for i in range(5): yield self.softMaster.sendBit(randBool()) yield self.softMaster.sendStop()
def spiSlaveAgent(spi, queue, clk): global sclkStable global mosiStable global ssStable global sclkStableLast global mosiStableLast global ssStableLast @coroutine def wait(cycles): global sclkStable global mosiStable global ssStable global sclkStableLast global mosiStableLast global ssStableLast sclkLast = str(spi.sclk) mosiLast = str(spi.mosi) ssLast = str(spi.ss) for i in range(cycles): yield RisingEdge(clk) sclkNew = str(spi.sclk) mosiNew = str(spi.mosi) ssNew = str(spi.ss) sclkStable += 1 mosiStable += 1 ssStable += 1 if sclkNew != sclkLast: sclkStableLast = sclkStable sclkStable = 0 if mosiNew != mosiLast: mosiStableLast = mosiStable mosiStable = 0 if ssNew != ssLast: ssStableLast = ssStable ssStable = 0 sclkLast = sclkNew mosiLast = mosiNew ssLast = ssNew ssValue = 0xF while True: if queue.empty(): yield wait(1) # assert(sclkStable > 1) # assert(mosiStable > 1) # assert(ssStable > 1) else: head = queue.get() if isinstance(head, SlaveCmdData): for i in range(8): if spiConfig.cpha == False: spi.miso <= testBit( head.slaveData, 7 - i) if head.slaveData != None else randBool() while True: yield wait(1) if spi.sclk == (not spiConfig.cpol): break assert sclkStableLast >= spiConfig.sclkToggle assert mosiStable >= spiConfig.sclkToggle assertEquals(spi.mosi, testBit(head.masterData, 7 - i), "MOSI mismatch") while True: yield wait(1) if spi.sclk == (spiConfig.cpol): break assert sclkStableLast >= spiConfig.sclkToggle else: while True: yield wait(1) if spi.sclk == (not spiConfig.cpol): break spi.miso <= testBit( head.slaveData, 7 - i) if head.slaveData != None else randBool() assert sclkStableLast >= spiConfig.sclkToggle while True: yield wait(1) if spi.sclk == (spiConfig.cpol): break assert mosiStable >= spiConfig.sclkToggle assert sclkStableLast >= spiConfig.sclkToggle assertEquals(spi.mosi, testBit(head.masterData, 7 - i), "MOSI mismatch") elif isinstance(head, SlaveCmdSs): while True: yield wait(1) assert sclkStable > 0 if spi.ss != ssValue: break if head.enable: yield wait(spiConfig.ssSetup - 1) print(str(ssStable) + " " + str(sclkStable)) assert ssStable >= spiConfig.ssSetup - 1 assert sclkStable >= spiConfig.ssSetup - 1 else: print(str(ssStableLast) + " " + str(sclkStable)) assert ssStableLast >= spiConfig.ssHold assert sclkStable >= spiConfig.ssHold yield wait(spiConfig.ssDisable - 1) print(str(ssStable) + " " + str(sclkStable)) assert ssStable >= spiConfig.ssDisable - 1 assert sclkStable >= spiConfig.ssDisable - 1 assertEquals(spi.ss, setBit(ssValue, head.index, not head.enable), "SS mismatch") ssValue = int(spi.ss)
def SlaveThread(scl,sda,clk,baudPeriod): global crapyConflictCounter global normalConflictCounter global normalTransactionCounter log.debug("x") IDLE = 0 START = 1 DATA = 2 state = IDLE dataState = 0 scl.write(True) sda.write(True) sclLast = True sdaLast = True while True: yield RisingEdge(clk) sclValue = scl.read() sdaValue = sda.read() sclRising = sclValue and not sclLast sclFalling = not sclValue and sclLast sdaRising = sdaValue and not sdaLast sdaFalling = not sdaValue and sdaLast sclLast = sclValue sdaLast = sdaValue if state == IDLE: if sdaFalling and sclValue: state = START elif state == START: if sclFalling: state = DATA dataState = 0 address = 0 elif state == DATA: if sclRising: if dataState < 8: address |= sdaValue << (7-dataState) elif sclFalling: dataState += 1 if dataState >= 8 and dataState < 16: if random.random() < 0.2: #Clock stretching scl.write(False) yield Timer(randInt(baudPeriod/10, baudPeriod*10)) sda.write((cmdToData[address] >> (15-dataState)) & 1) yield Timer(baudPeriod/4); scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) sclLast = False else: sda.write((cmdToData[address] >> (15 - dataState)) & 1) elif(dataState == 6 and random.random() < 0.2): scl.write(False) if random.random() < 0.2: # Clock stretching yield Timer(randInt(baudPeriod / 10, baudPeriod * 10)) yield Timer(baudPeriod / 2) sda.write(False) yield Timer(baudPeriod / 2) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) yield Timer(baudPeriod) if random.random() < 0.5: #Normal conflict normalConflictCounter += 1 for i in range(4): rand = randBool() scl.write(False) yield Timer(baudPeriod/2) sda.write(rand) yield Timer(baudPeriod/2) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) yield Timer(baudPeriod) assert sda.read() == rand scl.write(False) yield Timer(baudPeriod / 2) sda.write(False) yield Timer(baudPeriod / 2) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) yield Timer(baudPeriod) sda.write(True) else: #crapy conflict wihtout STOP crapyConflictCounter += 1 scl.write(False) yield Timer(baudPeriod / 2) sda.write(True) yield Timer(baudPeriod / 2) scl.write(True) yield clockedFuncWaitTrue(clk, scl.read) yield Timer(baudPeriod) state = IDLE continue else: if random.random() < 0.2: #Clock stretching scl.write(False) yield Timer(randInt(baudPeriod/10, baudPeriod*10)) sda.write(True) yield Timer(baudPeriod/4); scl.write(True) sclLast = False else: sda.write(True) elif sclValue: if sdaRising: state = 0 if sdaFalling: state = 1 pass
def run(self): global crapyConflictCounter global normalConflictCounter global normalTransactionCounter yield Timer(self.baudPeriod * 10) while crapyConflictCounter < 2 or normalConflictCounter < 3 or normalTransactionCounter < 40: while True: colision = False cmd = Transaction() cmd.mode = 0 cmd.data = randBool() self.cmdQueue.append(cmd) address = randBits(8) | 2 for bitId in range(8): cmd = Transaction() cmd.mode = 1 cmd.data = (address >> (7 - bitId)) & 1 self.cmdQueue.append(cmd) yield clockedWaitTrue(self.clk,self.rsp.valid) if self.rsp.payload.data != cmd.data: assert bitId == 6 colision = True cmd = Transaction() cmd.mode = 3 #DROP cmd.data = randBool() self.cmdQueue.append(cmd) break if colision: continue for bitId in range(8): cmd = Transaction() cmd.mode = 1 cmd.data = True self.cmdQueue.append(cmd) yield clockedWaitTrue(self.clk,self.rsp.valid) assert self.rsp.payload.data == ((cmdToData[address] >> (7-bitId)) & 1) if random.random() < 0.75: cmd = Transaction() cmd.mode = 2 cmd.data = randBool() self.cmdQueue.append(cmd) if random.random() < 0.75: #no other master frame if random.random() < 0.5: # With inter frame delay yield Timer(randInt(0,self.baudPeriod*20)) else: @coroutine def anotherFrameEmiter(): yield self.softMaster.sendStart() for i in range(5): yield self.softMaster.sendBit(randBool()) yield self.softMaster.sendStop() yield Timer(randInt(self.baudPeriod * 4, self.baudPeriod * 10)) fork(anotherFrameEmiter()) yield Timer(randInt(self.baudPeriod * 1, self.baudPeriod * 14)) normalTransactionCounter += 1 break while self.cmdQueue: yield Timer(self.baudPeriod * 10)
def spiSlaveAgent(spi, queue, clk): global sclkStable global mosiStable global ssStable global sclkStableLast global mosiStableLast global ssStableLast @coroutine def wait(cycles): global sclkStable global mosiStable global ssStable global sclkStableLast global mosiStableLast global ssStableLast sclkLast = str(spi.sclk) mosiLast = str(spi.mosi) ssLast = str(spi.ss) for i in xrange(cycles): yield RisingEdge(clk) sclkNew = str(spi.sclk) mosiNew = str(spi.mosi) ssNew = str(spi.ss) sclkStable += 1 mosiStable += 1 ssStable += 1 if sclkNew != sclkLast: sclkStableLast = sclkStable sclkStable = 0 if mosiNew != mosiLast: mosiStableLast = mosiStable mosiStable = 0 if ssNew != ssLast: ssStableLast = ssStable ssStable = 0 sclkLast = sclkNew mosiLast = mosiNew ssLast = ssNew ssValue = 0xF while True: if queue.empty(): yield wait(1) # assert(sclkStable > 1) # assert(mosiStable > 1) # assert(ssStable > 1) else: head = queue.get() if isinstance(head, SlaveCmdData): for i in xrange(8): if spiConfig.cpha == False: spi.miso <= testBit(head.slaveData, 7-i) if head.slaveData != None else randBool() while True: yield wait(1) if spi.sclk == (not spiConfig.cpol): break assert sclkStableLast >= spiConfig.sclkToogle assert mosiStable >= spiConfig.sclkToogle assertEquals(spi.mosi, testBit(head.masterData, 7-i),"MOSI missmatch") while True: yield wait(1) if spi.sclk == (spiConfig.cpol): break assert sclkStableLast >= spiConfig.sclkToogle else: while True: yield wait(1) if spi.sclk == (not spiConfig.cpol): break spi.miso <= testBit(head.slaveData, 7 - i) if head.slaveData != None else randBool() assert sclkStableLast >= spiConfig.sclkToogle while True: yield wait(1) if spi.sclk == (spiConfig.cpol): break assert mosiStable >= spiConfig.sclkToogle assert sclkStableLast >= spiConfig.sclkToogle assertEquals(spi.mosi, testBit(head.masterData, 7 - i), "MOSI missmatch") elif isinstance(head, SlaveCmdSs): while True: yield wait(1) assert sclkStable > 0 if spi.ss != ssValue: break if head.enable: yield wait(spiConfig.ssSetup-1) print str(ssStable) + " " + str(sclkStable) assert ssStable >= spiConfig.ssSetup-1 assert sclkStable >= spiConfig.ssSetup-1 else: print str(ssStableLast) + " " + str(sclkStable) assert ssStableLast >= spiConfig.ssHold assert sclkStable >= spiConfig.ssHold yield wait(spiConfig.ssDisable-1) print str(ssStable) + " " + str(sclkStable) assert ssStable >= spiConfig.ssDisable-1 assert sclkStable >= spiConfig.ssDisable-1 assertEquals(spi.ss, setBit(ssValue, head.index, not head.enable), "SS mismatch") ssValue = int(spi.ss)