def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset, 100000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
baudPeriod = 2500000
sclInterconnect = OpenDrainInterconnect()
sclInterconnect.addHardDriver(dut.io_i2c_scl_write)
sclInterconnect.addHardReader(dut.io_i2c_scl_read)
sdaInterconnect = OpenDrainInterconnect()
sdaInterconnect.addHardDriver(dut.io_i2c_sda_write)
sdaInterconnect.addHardReader(dut.io_i2c_sda_read)
dut.io_config_samplingClockDivider <= 3
dut.io_config_timerClockDivider <= 24
softMaster = I2cSoftMaster(sclInterconnect.newSoftConnection(),
sdaInterconnect.newSoftConnection(), baudPeriod,
dut.clk)
slaveThread = fork(
SlaveThread(sclInterconnect.newSoftConnection(),
sdaInterconnect.newSoftConnection(), dut.clk, baudPeriod))
masterThread = fork(
MasterThread(Stream(dut, "io_cmd"), Flow(dut, "io_rsp"), dut.clk,
dut.reset, baudPeriod, softMaster).run())
yield masterThread.join()
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset, 1000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
# cocotb.fork(SimulationTimeout(1000 * 20e3))
cocotb.fork(debugFilter(dut))
dut.io_parallelIn <= 0x10
for i in xrange(200):
yield RisingEdge(dut.clk)
dut.io_parallelIn <= 0x70
for i in xrange(1000):
yield RisingEdge(dut.clk)
dut.io_parallelIn <= 0x80
for i in xrange(1000):
yield RisingEdge(dut.clk)
dut.io_parallelIn <= 0x90
for i in xrange(1000):
yield RisingEdge(dut.clk)
dut.io_parallelIn <= 0xF0
for i in xrange(200):
yield RisingEdge(dut.clk)
def jtagTest(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(simulationSpeedPrinter(dut.io_axiClk))
yield loadIHex(dut,"e:/vm/share/pinsec_test.hex",dut.io_axiClk,dut.io_asyncReset)
cocotb.fork(ClockDomainAsyncReset(dut.io_axiClk, dut.io_asyncReset))
jtag = JtagMaster(Bundle(dut,"io_jtag"),4000,4)
yield Timer(1000*50)
yield jtag.goToIdle()
yield Timer(1000*8)
# Check rom write/read via jtag
yield jtagBridgeWrite(jtag,0x3000,0x11223344,4)
yield jtagBridgeWrite(jtag,0x3002,0x00550000,1)
yield jtagBridgeReadAssert(jtag,0x3000,4,0x11553344)
yield jtagBridgeReadAssert(jtag,0x3002,2,0x1155)
# Check RISCV APB debug module via jtag
yield jtagBridgeWrite(jtag,0xF00F0200,1 << 17,4) #halt CPU
yield jtagBridgeReadAssert(jtag,0xF00F0200,4,(1 << 1),0x0F)
yield jtagBridgeWrite(jtag,0xF00F0008,0x99887766,4) #write R2
yield jtagBridgeReadAssert(jtag,0xF00F0008,4,0x99887766)
yield Timer(1000*500)
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
drivers = []
checkers = []
for i in range(3):
readQueue = Queue()
ahb = Bundle(dut, "ahbMasters_" + str(i))
drivers.append(AhbLite3MasterDriver(ahb, AhbLite3TraficGeneratorWithMemory(12, 32,readQueue,i), dut.clk, dut.reset))
checkers.append(AhbLite3MasterReadChecker(ahb, readQueue, dut.clk, dut.reset))
# AhbLite3MasterIdle(Bundle(dut, "ahbMasters_1"))
# AhbLite3MasterIdle(Bundle(dut, "ahbMasters_2"))
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_0"), 0x000, 0x400, dut.clk, dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_1"), 0x400, 0x400, dut.clk, dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_2"), 0x800, 0x400, dut.clk, dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_3"), 0xC00, 0x400, dut.clk, dut.reset)
while True:
yield RisingEdge(dut.clk)
done = True
for checker in checkers:
if checker.counter < 1000:
done = False
if done:
break
dut.log.info("Cocotb test done")
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset,1000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000*20e3))
apb = Apb3(dut, "io_apb", dut.clk)
apb.idle()
spi = SpiSlave(dut, "io_spi")
spiCtrl = SpiSlaveMaster(spi)
yield Timer(5000)
yield RisingEdge(dut.clk)
yield testIt(apb,dut.io_interrupt, spiCtrl, 0, 0)
yield restart(dut)
yield testIt(apb,dut.io_interrupt, spiCtrl, 0, 1)
yield restart(dut)
yield testIt(apb,dut.io_interrupt, spiCtrl, 1, 0)
yield restart(dut)
yield testIt(apb,dut.io_interrupt, spiCtrl, 1, 1)
def test1(dut):
random.seed(0)
uut = dut.uut
cocotb.fork(simulationSpeedPrinter(uut.io_axiClk))
yield loadIHex(uut,"../hex/vga.hex",uut.io_axiClk,uut.io_asyncReset)
pinsecClockGen(dut)
yield assertions(uut)
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset, 1000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
# cocotb.fork(SimulationTimeout(1000 * 20e3))
dut.io_step <= 1
for i in xrange(8000):
yield RisingEdge(dut.clk)
def test1(dut):
random.seed(0)
uut = dut.uut
cocotb.fork(simulationSpeedPrinter(uut.io_axiClk))
yield loadIHex(uut,"../hex/vga.hex",uut.io_axiClk,uut.io_asyncReset)
pinsecClockGen(dut)
yield assertions(uut)
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset, 1000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
dut.io_en <= False
for i in xrange(20):
yield RisingEdge(dut.clk)
dut.io_en <= True
dut.io_step <= 40
for i in xrange(8000):
yield RisingEdge(dut.clk)
def test1(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(simulationSpeedPrinter(dut.io_axiClk))
yield loadIHex(dut, "../hex/timer.hex", dut.io_axiClk, dut.io_asyncReset)
cocotb.fork(ClockDomainAsyncReset(dut.io_axiClk, dut.io_asyncReset))
yield assertions(dut)
yield Timer(1000 * 10)
dut.log.info("Cocotb test done")
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000*16000))
yield driveAndCheck(dut, "setValueA",0x11,8,dut.io_valueA)
yield driveAndCheck(dut, "setValueB", 0x22334455, 32, dut.io_valueB)
yield driveAndCheck(dut, "setValueC", 0x66778899AABB, 48, dut.io_valueC)
yield driveAndCheck(dut, "setValueB", 0xCAFEF00D, 32, dut.io_valueB)
yield Timer(1000*20)
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
uut = dut.uut
cocotb.fork(simulationSpeedPrinter(uut.io_axiClk))
yield loadIHex(dut,"../hex/uart.hex",uut.io_axiClk,uut.io_asyncReset)
pinsecClockGen(dut)
cocotb.fork(txToRxBypass(uut))
yield assertions(uut)
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*1000)
SdramTester("sdramTester",phaseManager,Stream(dut,"io_bus_cmd"),Stream(dut,"io_bus_rsp"),dut.clk,dut.reset)
yield phaseManager.run()
def test1(dut):
random.seed(0)
uut = dut.uut
log = open('uartTx.log', 'w')
cocotb.fork(simulationSpeedPrinter(uut.io_axiClk))
yield loadIHex(dut,"../hex/dhrystone.hex",uut.io_axiClk,uut.io_asyncReset)
pinsecClockGen(dut)
cocotb.fork(uartTxBypass(uut.axi_uartCtrl.uartCtrl,uut.io_axiClk,log))
yield assertions(uut,log)
yield Timer(1000*10)
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*2000)
checker = Axi4SharedMemoryChecker("checker",phaseManager,Axi4Shared(dut, "io_axi"),12,dut.clk,dut.reset)
checker.idWidth = 2
checker.nonZeroReadRspCounterTarget = 2000
yield phaseManager.run()
def test1(dut):
dut.log.info("Cocotb test boot")
queueTx = Queue()
queueRx = Queue()
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(sendRandomPackets(dut, queueTx, queueRx))
cocotb.fork(checkTx(dut,queueTx))
cocotb.fork(txToRxBypass(dut))
cocotb.fork(simulationSpeedPrinter(dut.clk))
yield checkCtrlReadedBytes(dut, queueRx)
dut.log.info("Cocotb test done")
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000 * 2000))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 200)
DriverAgent("driver", phaseManager, dut)
MonitorAgent("monitor", phaseManager, dut)
yield phaseManager.run()
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 1000)
SdramTester("sdramTester", phaseManager, Stream(dut, "io_bus_cmd"),
Stream(dut, "io_bus_rsp"), dut.clk, dut.reset)
yield phaseManager.run()
def do(self,iHexPath):
loadIHex(iHexPath, self.rom)
cocotb.fork(simulationSpeedPrinter(self.dut.clk))
cocotb.fork(ClockDomainAsyncReset(self.dut.clk, self.dut.reset))
cocotb.fork(self.driveMisc())
cocotb.fork(self.driveIRsp())
cocotb.fork(self.driveDRsp())
while True:
yield RisingEdge(self.dut.clk)
if int(self.dut.io_d_cmd_valid) == 1 and int(self.dut.io_d_cmd_payload_address) == 0xFFFFFFFC:
if int(self.dut.io_d_cmd_payload_data) != 0x00000001:
print("ERROR")
raise TestFailure("RISCV test %s fail with %d" % (iHexPath,int(self.dut.io_d_cmd_payload_data)))
else:
raise TestSuccess("RISCV test %s pass with %d" % (iHexPath, int(self.dut.io_d_cmd_payload_data)))
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*200)
StreamFifoTester("fifoA",phaseManager,Stream(dut,"fifoAPush"),Stream(dut,"fifoAPop"),bundleAGen,3000,dut.clk,dut.reset).createInfrastructure()
StreamFifoTester("fifoB",phaseManager,Stream(dut,"fifoBPush"),Stream(dut,"fifoBPop"),bundleAGen,3000,dut.clk,dut.reset).createInfrastructure()
yield phaseManager.run()
def jtagTest(dut):
from cocotblib.misc import cocotbXHack
cocotbXHack()
uut = dut.uut
log = open('uartTx.log', 'w')
cocotb.fork(simulationSpeedPrinter(uut.io_axiClk))
yield loadIHex(dut,"../hex/dummy.hex",uut.io_axiClk,uut.io_asyncReset)
pinsecClockGen(dut)
yield Timer(1000*10)
jtag = JtagMaster(Bundle(uut,"io_jtag"),20000*4,4)
yield Timer(1000*50)
yield jtag.goToIdle()
yield Timer(1000*8)
#yield jtagBridgeWrite(jtag,0xF00F0200,0x00030000,4)
#yield Timer(1000*80)
# Check rom write/read via jtag
yield jtagBridgeWrite(jtag,8,0x11223344,4)
yield jtagBridgeWrite(jtag,10,0x00550000,1)
yield jtagBridgeReadAssert(jtag,8,4,0x11553344)
yield jtagBridgeReadAssert(jtag,10,2,0x1155)
yield jtagBridgeWrite(jtag,0x40004FF0,0x77665544,4)
yield Timer(1000*50)
yield jtagBridgeReadAssert(jtag,0x40004FF0,4,0x77665544)
yield jtagBridgeWrite(jtag,0x40004FF2,0x00FF0000,1)
yield Timer(1000*50)
yield jtagBridgeReadAssert(jtag,0x40004FF0,4,0x77FF5544)
# Check RISCV APB debug module via jtag
yield jtagBridgeWrite(jtag,0xF00F0200,1 << 17,4) #halt CPU
yield jtagBridgeReadAssert(jtag,0xF00F0200,4,(1 << 1),0x0F)
yield jtagBridgeWrite(jtag,0xF00F0008,0x99887766,4) #write R2
yield jtagBridgeReadAssert(jtag,0xF00F0008,4,0x99887766)
yield jtagBridgeReadAssert(jtag,0xF00F0000+10*4,4,0x55) #Written by dummy.hex
yield Timer(1000*500)
def test1(dut):
from cocotblib.misc import cocotbXHack
cocotbXHack()
random.seed(0)
uut = dut.uut
log = open('uartTx.log', 'w')
cocotb.fork(simulationSpeedPrinter(uut.io_axiClk))
yield loadIHex(dut, "../hex/dhrystone.hex", uut.io_axiClk,
uut.io_asyncReset)
pinsecClockGen(dut)
cocotb.fork(uartTxBypass(uut.axi_uartCtrl.uartCtrl, uut.io_axiClk, log))
yield assertions(uut, log)
yield Timer(1000 * 10)
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
queueTx = Queue()
queueRx = Queue()
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(sendRandomPackets(dut, queueTx, queueRx))
cocotb.fork(checkTx(dut, queueTx))
cocotb.fork(txToRxBypass(dut))
cocotb.fork(simulationSpeedPrinter(dut.clk))
yield checkCtrlReadedBytes(dut, queueRx)
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
random.seed(0)
cocotb.fork(simulationSpeedPrinter(dut.clk))
# elements = [a for a in dut.AhbRam if a._name.startswith("")]
# for e in elements:
# print(str(e._name))
# while True:
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.ram_port1_mask <= 0xF
# dut.AhbRam.ram_port1_address <= 0X90
# dut.AhbRam.ram_port1_data <= 0xCAFEF00D
#
# dut.AhbRam.reset <= 1
# dut.AhbRam.ram_port1_enable <= 1
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.clk <= 0
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.clk <= 1
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 0
# yield Timer(1000)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
readQueue = Queue()
ahb = Bundle(dut, "ahb")
driver = AhbLite3MasterDriver(ahb, AhbLite3TraficGeneratorWithMemory(10, 32,readQueue), dut.clk, dut.reset)
checker = AhbLite3MasterReadChecker(ahb, readQueue, dut.clk, dut.reset)
terminaison = AhbLite3Terminaison(ahb, dut.clk, dut.reset)
while True:
yield RisingEdge(dut.clk)
if checker.counter > 4000:
break
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
random.seed(0)
cocotb.fork(simulationSpeedPrinter(dut.clk))
# elements = [a for a in dut.AhbRam if a._name.startswith("")]
# for e in elements:
# print(str(e._name))
# while True:
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.ram_port1_mask <= 0xF
# dut.AhbRam.ram_port1_address <= 0X90
# dut.AhbRam.ram_port1_data <= 0xCAFEF00D
#
# dut.AhbRam.reset <= 1
# dut.AhbRam.ram_port1_enable <= 1
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.clk <= 0
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.clk <= 1
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 0
# yield Timer(1000)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
readQueue = Queue()
ahb = Bundle(dut, "ahb")
driver = AhbLite3MasterDriver(
ahb, AhbLite3TraficGeneratorWithMemory(10, 32, readQueue), dut.clk,
dut.reset)
checker = AhbLite3MasterReadChecker(ahb, readQueue, dut.clk, dut.reset)
terminaison = AhbLite3Terminaison(ahb, dut.clk, dut.reset)
while True:
yield RisingEdge(dut.clk)
if checker.counter > 4000:
break
dut.log.info("Cocotb test done")
def jtagTest(dut):
from cocotblib.misc import cocotbXHack
cocotbXHack()
uut = dut.uut
log = open('uartTx.log', 'w')
cocotb.fork(simulationSpeedPrinter(uut.io_axiClk))
yield loadIHex(dut, "../hex/dummy.hex", uut.io_axiClk, uut.io_asyncReset)
pinsecClockGen(dut)
yield Timer(1000 * 10)
jtag = JtagMaster(Bundle(uut, "io_jtag"), 20000 * 4, 4)
yield Timer(1000 * 50)
yield jtag.goToIdle()
yield Timer(1000 * 8)
#yield jtagBridgeWrite(jtag,0xF00F0200,0x00030000,4)
#yield Timer(1000*80)
# Check rom write/read via jtag
yield jtagBridgeWrite(jtag, 8, 0x11223344, 4)
yield jtagBridgeWrite(jtag, 10, 0x00550000, 1)
yield jtagBridgeReadAssert(jtag, 8, 4, 0x11553344)
yield jtagBridgeReadAssert(jtag, 10, 2, 0x1155)
yield jtagBridgeWrite(jtag, 0x40004FF0, 0x77665544, 4)
yield Timer(1000 * 50)
yield jtagBridgeReadAssert(jtag, 0x40004FF0, 4, 0x77665544)
yield jtagBridgeWrite(jtag, 0x40004FF2, 0x00FF0000, 1)
yield Timer(1000 * 50)
yield jtagBridgeReadAssert(jtag, 0x40004FF0, 4, 0x77FF5544)
# Check RISCV APB debug module via jtag
yield jtagBridgeWrite(jtag, 0xF00F0200, 1 << 17, 4) #halt CPU
yield jtagBridgeReadAssert(jtag, 0xF00F0200, 4, (1 << 1), 0x0F)
yield jtagBridgeWrite(jtag, 0xF00F0008, 0x99887766, 4) #write R2
yield jtagBridgeReadAssert(jtag, 0xF00F0008, 4, 0x99887766)
yield jtagBridgeReadAssert(jtag, 0xF00F0000 + 10 * 4, 4,
0x55) #Written by dummy.hex
yield Timer(1000 * 500)
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 2000)
checker = Axi4SharedMemoryChecker("checker", phaseManager,
Axi4Shared(dut, "io_axi"), 12, dut.clk,
dut.reset)
checker.idWidth = 2
checker.nonZeroReadRspCounterTarget = 2000
yield phaseManager.run()
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
bmbs = [Bmb(dut, "io_ports_" + str(x)) for x in range(3)]
tester = BmbMemoryTester(bmbs, 16*1024, 2, 32,dut.clk,dut.reset)
@cocotb.coroutine
def delay():
yield RisingEdge(dut.clk)
apb = Apb3(dut, "io_apb", dut.clk)
yield apb.write(0x10, 0x30d)
yield apb.write(0x20, 0x1060103)
yield apb.write(0x24, 0x1)
yield apb.write(0x28, 0x1000004)
yield apb.write(0x10c, 0x0)
yield apb.write(0x108, 0x400)
yield apb.write(0x104, 0x8)
yield apb.write(0x100, 0x0)
yield apb.write(0x10c, 0x0)
yield apb.write(0x108, 0x0)
yield apb.write(0x104, 0x10)
yield apb.write(0x100, 0x0)
yield apb.write(0x10c, 0x0)
yield apb.write(0x108, 0x0)
yield apb.write(0x104, 0x10)
yield apb.write(0x100, 0x0)
yield apb.write(0x10c, 0x0)
yield apb.write(0x108, 0x20)
yield apb.write(0x104, 0x0)
yield apb.write(0x100, 0x0)
delay()
tester.run = True
while True:
yield Timer(0x1000000)
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*200)
checker = Axi4SharedMemoryChecker("checker",phaseManager,Axi4Shared(dut, "io_axi"),12,dut.clk,dut.reset)
checker.idWidth = 2
checker.nonZeroReadRspCounterTarget = 2000
yield phaseManager.run()
dut.log.info("Cocotb test done")
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset,1000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000*20e3))
apb = Apb3(dut, "io_apb", dut.clk)
apb.idle()
spi = SpiMaster(dut, "io_spi")
slaveQueue = Queue()
yield Timer(5000)
yield RisingEdge(dut.clk)
apbThread = fork(apbAgent(apb,slaveQueue))
spiThread = fork(spiSlaveAgent(spi,slaveQueue, dut.clk))
yield apbThread.join()
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset, 1000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000 * 20e3))
apb = Apb3(dut, "io_apb", dut.clk)
apb.idle()
spi = SpiMaster(dut, "io_spi")
slaveQueue = Queue()
yield Timer(5000)
yield RisingEdge(dut.clk)
apbThread = fork(apbAgent(apb, slaveQueue))
spiThread = fork(spiSlaveAgent(spi, slaveQueue, dut.clk))
yield apbThread.join()
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 200)
StreamFifoTester("fifoA", phaseManager, Stream(dut, "fifoAPush"),
Stream(dut, "fifoAPop"), bundleAGen, 3000, dut.clk,
dut.reset).createInfrastructure()
StreamFifoTester("fifoB", phaseManager, Stream(dut, "fifoBPush"),
Stream(dut, "fifoBPop"), bundleAGen, 3000, dut.clk,
dut.reset).createInfrastructure()
yield phaseManager.run()
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000 * 8000))
axiLite = AxiLite4(dut, "io_axiLite")
master = AxiLite4Master(axiLite, dut.clk, dut.reset)
yield RisingEdge(dut.clk)
yield master.readAssert(
0x00, 0, 1,
"wavePlayer.phase.run was read as True, but should be False")
yield master.readAssert(
0x10, 1, 1,
"wavePlayer.filter.bypass was read as False, but should be True")
yield master.write(4, 0x80)
yield master.write(0, 1)
yield master.readAssert(
0x00, 1, 1,
"wavePlayer.phase.run was read as False, but should be True")
phaseValue = 0
for i in range(4):
newValue = [0]
yield master.read(0x8, newValue)
assert newValue[
0] > phaseValue, "wavePlayer.phase.value doesn't seem to increment"
phaseValue = newValue[0]
yield RisingEdge(dut.clk)
yield analyseFreq(dut, 0x200)
yield Timer(1000 * 2000)
yield master.write(0x14, 0x10)
yield master.write(0x10, 0)
yield master.readAssert(
0x10, 0, 1,
"wavePlayer.filter.bypass was read as True, but should be False")
yield Timer(1000 * 2000)
yield analyseFreq(dut, 0x200)
yield Timer(1000 * 2000)
def do(self, iHexPath):
loadIHex(iHexPath, self.rom)
cocotb.fork(simulationSpeedPrinter(self.dut.clk))
cocotb.fork(ClockDomainAsyncReset(self.dut.clk, self.dut.reset))
cocotb.fork(self.driveMisc())
cocotb.fork(self.driveIRsp())
cocotb.fork(self.driveDRsp())
while True:
yield RisingEdge(self.dut.clk)
if int(self.dut.io_d_cmd_valid) == 1 and int(
self.dut.io_d_cmd_payload_address) == 0xFFFFFFFC:
if int(self.dut.io_d_cmd_payload_data) != 0x00000001:
print("ERROR")
raise TestFailure(
"RISCV test %s fail with %d" %
(iHexPath, int(self.dut.io_d_cmd_payload_data)))
else:
raise TestSuccess(
"RISCV test %s pass with %d" %
(iHexPath, int(self.dut.io_d_cmd_payload_data)))
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset,100000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
baudPeriod = 2500000
sclInterconnect = OpenDrainInterconnect()
sclInterconnect.addHardDriver(dut.io_i2c_scl_write)
sclInterconnect.addHardReader(dut.io_i2c_scl_read)
sdaInterconnect = OpenDrainInterconnect()
sdaInterconnect.addHardDriver(dut.io_i2c_sda_write)
sdaInterconnect.addHardReader(dut.io_i2c_sda_read)
dut.io_config_samplingClockDivider <= 3
dut.io_config_timerClockDivider <= 24
softMaster = I2cSoftMaster(sclInterconnect.newSoftConnection(), sdaInterconnect.newSoftConnection(), baudPeriod,dut.clk)
slaveThread = fork(SlaveThread(sclInterconnect.newSoftConnection(), sdaInterconnect.newSoftConnection(),dut.clk,baudPeriod))
masterThread = fork(MasterThread(Stream(dut,"io_cmd"),Flow(dut,"io_rsp"), dut.clk, dut.reset, baudPeriod,softMaster).run())
yield masterThread.join()
def test1(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
drivers = []
checkers = []
for i in range(3):
readQueue = Queue()
ahb = Bundle(dut, "ahbMasters_" + str(i))
drivers.append(
AhbLite3MasterDriver(
ahb, AhbLite3TraficGeneratorWithMemory(12, 32, readQueue, i),
dut.clk, dut.reset))
checkers.append(
AhbLite3MasterReadChecker(ahb, readQueue, dut.clk, dut.reset))
# AhbLite3MasterIdle(Bundle(dut, "ahbMasters_1"))
# AhbLite3MasterIdle(Bundle(dut, "ahbMasters_2"))
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_0"), 0x000, 0x400, dut.clk,
dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_1"), 0x400, 0x400, dut.clk,
dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_2"), 0x800, 0x400, dut.clk,
dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_3"), 0xC00, 0x400, dut.clk,
dut.reset)
while True:
yield RisingEdge(dut.clk)
done = True
for checker in checkers:
if checker.counter < 1000:
done = False
if done:
break
dut.log.info("Cocotb test done")
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000 * 8000))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 200)
driver = DriverAgent("driver", phaseManager, dut)
monitor = MonitorAgent("monitor", phaseManager, dut)
for i in range(1 << 8):
dut.io_memWrite_valid <= 1
dut.io_memWrite_payload_address <= i
dut.io_memWrite_payload_data <= randBits(32)
yield RisingEdge(dut.clk)
dut.io_memWrite_valid <= 0
driver.memInitDone = True
yield phaseManager.run()
def test1(dut):
random.seed(0)
import time
clkTocken = [1000]
sock = socket.socket(
socket.AF_INET, # Internet
socket.SOCK_DGRAM) # UDP
sock.setsockopt(SOL_SOCKET, SO_REUSEADDR, 1)
sock.setsockopt(SOL_SOCKET, SO_BROADCAST, 1)
sock.bind(('', SERVER_PORT))
cocotb.fork(ClockDomainAsyncResetTokened(dut.clk, dut.reset, clkTocken))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 200)
DriverAgent("driver", phaseManager, dut, sock, clkTocken)
MonitorAgent("monitor", phaseManager, dut, sock)
yield phaseManager.run()
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset,100000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(2000 * 2.5e6))
sclInterconnect = OpenDrainInterconnect()
sclInterconnect.addHardDriver(dut.io_i2c_scl_write)
sclInterconnect.addHardReader(dut.io_i2c_scl_read)
sdaInterconnect = OpenDrainInterconnect()
sdaInterconnect.addHardDriver(dut.io_i2c_sda_write)
sdaInterconnect.addHardReader(dut.io_i2c_sda_read)
softMaster = I2cSoftMaster(sclInterconnect.newSoftConnection(), sdaInterconnect.newSoftConnection(), 2500000,dut.clk)
apb = Apb3(dut, "io_apb", dut.clk)
apb.idle()
@coroutine
def txData(valid = False, enable = False, value = 0xFF, repeat = False, disableOnConflict = False):
yield apb.write(0, (valid << 8) | (enable << 9) | (value << 0) | (repeat << 10) | (disableOnConflict << 11))
@coroutine
def txAck(valid=False, enable=False, value=0x1, repeat=False, disableOnConflict=False):
yield apb.write(4, (valid << 8) | (enable << 9) | (value << 0) | (repeat << 10) | (disableOnConflict << 11))
@coroutine
def rxDataConfig(listen = False):
yield apb.write(8, listen << 9)
@coroutine
def rxAckConfig(listen = False):
yield apb.write(12, listen << 9)
@coroutine
def rxDataValue(expected):
yield apb.readAssertMasked(8, 0x100 | expected, 0x1FF)
@coroutine
def rxAckValue(expected):
yield apb.readAssertMasked(12, 0x100 | expected, 0x101)
@coroutine
def rxDataNotValid():
yield apb.readAssertMasked(8, 0, 0x100)
@coroutine
def rxAckNotValid():
yield apb.readAssertMasked(12, 0, 0x100)
@coroutine
def addressFilter(index, enable = False, is10Bits = False, value = 0):
yield apb.write(136+index*4, (enable << 15) | (is10Bits << 14) | (value << 0))
@coroutine
def addressFilterHits(value):
yield apb.readAssertMasked(128, value, 0xFFFFFFFF)
@coroutine
def idle():
yield txData(valid = True, repeat = True)
yield txAck(valid=True, repeat=True)
yield rxDataConfig(listen=False)
yield rxAckConfig(listen=False)
buffer = [0]
yield apb.write(40, 3) #samplingClockDivider
yield apb.write(44, 25*20-1) #timeout
yield apb.write(48, 4) #tsuDat
#Check idle controller
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xAA, 0xAA)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x55, 0x55)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# Check simple txData
yield idle()
yield txData(valid = True, enable = True, value = 0x0F)
yield rxDataConfig(listen=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xAA, 0x0A)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield rxDataValue(0x0A)
yield rxDataNotValid();
yield softMaster.wait(5)
# Check simple txAck
yield idle()
yield txAck(valid=True, enable=True, value=False)
yield rxAckConfig(listen=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xFF, 0xFF)
yield softMaster.sendBitCheck(True, False)
yield rxAckValue(False)
yield txAck(valid=True, enable=True, value=True)
yield softMaster.sendByteCheck(0x00, 0x00)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield rxAckValue(True)
yield softMaster.wait(5)
# Check explicit idle controller
yield idle()
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xAA, 0xAA)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x55, 0x55)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# Check tx clock stretching
yield idle()
yield txData(valid=False)
yield txAck(valid=False)
yield softMaster.wait(2)
yield softMaster.sendStart()
txThread = fork(softMaster.sendByteCheck(0xAA, 0x0A))
yield softMaster.wait(10)
yield txData(valid = True, enable = True, value = 0x0F)
yield txThread.join()
txThread = fork(softMaster.sendBitCheck(True, False))
yield softMaster.wait(10)
yield txAck(valid=True, enable=True, value=False)
yield txThread.join()
txThread = fork(softMaster.sendByteCheck(0x55, 0x50))
yield softMaster.wait(10)
yield txData(valid = True, enable = True, value = 0xF0)
yield txThread.join()
txThread = fork(softMaster.sendBitCheck(True, False))
yield softMaster.wait(10)
yield txAck(valid=True, enable=True, value=False)
yield txThread.join()
yield txData(valid = True, enable = True, value = 0x8F)
yield txAck(valid=True, enable=True, value=True)
yield softMaster.sendByteCheck(0xF3, 0x83)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# Check rxData clock streching
yield idle()
yield rxDataConfig(listen=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x11, 0x11)
yield softMaster.sendBitCheck(False, False)
txThread = fork(softMaster.sendByteCheck(0x22, 0x22))
yield softMaster.wait(16)
yield rxDataValue(0x11)
yield txThread.join()
yield rxDataValue(0x22)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# Check rxAck clock streching
yield idle()
yield rxAckConfig(listen=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x11, 0x11)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x22, 0x22)
txThread = fork(softMaster.sendBitCheck(True, True))
yield softMaster.wait(16)
yield rxAckValue(False)
yield txThread.join()
yield rxAckValue(True)
yield softMaster.sendStop()
yield softMaster.wait(5)
#check txData repeat
yield idle()
yield txData(valid = True, enable = True, value = 0x0F,repeat = True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x33, 0x03)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x44, 0x04)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x55, 0x05)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# check txAck repeat
yield idle()
yield txAck(valid=True, enable=True, value=0x0, repeat=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x33, 0x33)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendByteCheck(0x44, 0x44)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendByteCheck(0x55, 0x55)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendStop()
yield softMaster.wait(5)
#Check address filter
yield idle()
yield addressFilter(index = 2, enable = True, is10Bits = False, value = 0x63)
yield addressFilter(index = 1, enable = True, is10Bits = True, value = 0x123)
for i in xrange(2):
#7bits
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x63*2, 0x63*2)
t = fork(softMaster.sendBitCheck(True, False))
yield softMaster.wait(5)
yield addressFilterHits(1 << 2)
yield txData(valid=True, enable=True, value=0xF0)
yield txAck(valid=True, enable=True, value=False)
yield t.join()
yield softMaster.sendByteCheck(0x44, 0x40)
yield txAck(valid=True, repeat=True)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
#10bits
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xF3,0xF3)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendByteCheck(0x23,0x23)
t = fork(softMaster.sendBitCheck(True, False))
yield softMaster.wait(5)
yield addressFilterHits(1 << 1)
yield txData(valid=True, enable=True, value=0xF0)
yield txAck(valid=True, enable=True, value=False)
yield t.join()
yield softMaster.sendByteCheck(0x44, 0x40)
yield txAck(valid=True, repeat=True)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
#10bits no trigger
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xF3,0xF3)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendByteCheck(0x54,0x54)
yield softMaster.sendBitCheck(True, True)
yield addressFilterHits(0 << 1)
yield softMaster.sendStop()
yield softMaster.wait(5)
#7bits no trigger
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x13,0x13)
yield softMaster.sendBitCheck(True, True)
yield addressFilterHits(0 << 1)
yield softMaster.sendStop()
yield softMaster.wait(5)
def test1(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
axiMasters = [Axi4(dut, "axiMasters_" + str(i)) for i in range(3)]
axiSlaves = [Axi4(dut, "axiSlaves_" + str(i)) for i in range(4)]
masterHandles = []
idToWrites = [[] for i in range(16)]
# Instanciate master side
for idx, axiMaster in enumerate(axiMasters):
masterHandle = MasterHandle(idx, idToWrites)
masterHandles.append(masterHandle)
# Read
StreamDriverMaster(axiMaster.ar, masterHandle.genReadCmd, dut.clk,
dut.reset)
StreamDriverSlave(axiMaster.r, dut.clk, dut.reset)
StreamMonitor(axiMaster.r, masterHandle.onReadRsp, dut.clk, dut.reset)
# Write
StreamDriverMaster(axiMaster.aw, masterHandle.genWriteCmd, dut.clk,
dut.reset)
StreamDriverMaster(axiMaster.w, masterHandle.genWriteData, dut.clk,
dut.reset)
StreamDriverSlave(axiMaster.b, dut.clk, dut.reset)
StreamMonitor(axiMaster.b, masterHandle.onWriteRsp, dut.clk, dut.reset)
# instanciate slave side
for idx, axiSlave in enumerate(axiSlaves):
axiSlave.r.payload.hid <= 0
axiSlave.b.payload.hid <= 0
slaveHandle = SlaveHandle(idx, idToWrites)
# Read
StreamDriverSlave(axiSlave.ar, dut.clk, dut.reset)
StreamDriverMaster(axiSlave.r, slaveHandle.genReadRsp, dut.clk,
dut.reset)
StreamMonitor(axiSlave.ar, slaveHandle.onReadCmd, dut.clk, dut.reset)
# Write
StreamMonitor(axiSlave.aw, slaveHandle.onWriteCmd, dut.clk, dut.reset)
StreamDriverSlave(axiSlave.aw, dut.clk, dut.reset)
StreamMonitor(axiSlave.w, slaveHandle.onWriteData, dut.clk, dut.reset)
StreamDriverSlave(axiSlave.w, dut.clk, dut.reset)
StreamDriverMaster(axiSlave.b, slaveHandle.genWriteRsp, dut.clk,
dut.reset)
# Run until completion
while True:
yield RisingEdge(dut.clk)
done = True
for handle in masterHandles:
if not handle.isCompleted():
done = False
for l in idToWrites:
if l:
done = False
if done:
break
yield Timer(1000 * 10)
dut.log.info("Cocotb test done")
def test1(dut):
# random.seed(13)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset,100000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
sclInterconnect = OpenDrainInterconnect()
sclInterconnect.addHardDriver(dut.io_i2c_scl_write)
sclInterconnect.addHardReader(dut.io_i2c_scl_read)
sdaInterconnect = OpenDrainInterconnect()
sdaInterconnect.addHardDriver(dut.io_i2c_sda_write)
sdaInterconnect.addHardReader(dut.io_i2c_sda_read)
dut.io_config_samplingClockDivider <= 3
dut.io_config_timeout <= 25*10-1
dut.io_config_tsuDat <= 4
softMaster = I2cSoftMaster(sclInterconnect.newSoftConnection(), sdaInterconnect.newSoftConnection(), 2500000,dut.clk)
masterCmds = []
slaveCmds = []
slaveRsps = []
masterRsps = []
masterCmds.append(10)
for frameId in range(50):
masterCmds.append("start")
slaveCmds.append("start")
while True:
for bitId in range(randInt(1,10)):
masterValue = random.uniform(0,1) > 0.5
slaveValue = random.uniform(0,1) > 0.5
slaveEnable = random.uniform(0,1) > 0.5
value = masterValue and (slaveValue or not slaveEnable)
masterCmds.append(masterValue)
slaveRsps.append(slaveValue if slaveEnable else "Z")
slaveCmds.append("drive")
slaveCmds.append(value)
masterRsps.append(value)
if random.uniform(0,1) < 0.1:
slaveCmds.append("drive")
slaveRsps.append(random.uniform(0,1) > 0.5)
masterCmds.append(20)
masterCmds.append("drop")
masterCmds.append(randInt(1,10))
slaveCmds.append("drop")
break
slaveRsps.append("Z")
if random.uniform(0,1) < 0.5:
masterCmds.append("stop")
slaveCmds.append("drive")
slaveCmds.append(False)
slaveCmds.append("stop")
masterCmds.append(randInt(1,10))
break
masterCmds.append("restart")
slaveCmds.append("drive")
slaveCmds.append(True)
slaveCmds.append("restart")
masterThread = fork(i2cMasterThread(softMaster, masterCmds,masterRsps))
slaveThread = fork(i2cSlaveThread(Bundle(dut,"io_bus_cmd"), Bundle(dut,"io_bus_rsp"),slaveCmds,slaveRsps, dut.clk))
yield masterThread.join()
cocotb.fork(SimulationTimeout(100 * 2500000))
while True:
if not slaveCmds and not slaveRsps and not masterRsps:
break
yield Timer(10000)
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset,100000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
sclInterconnect = OpenDrainInterconnect()
sclInterconnect.addHardDriver(dut.io_i2c_scl_write)
sclInterconnect.addHardReader(dut.io_i2c_scl_read)
sdaInterconnect = OpenDrainInterconnect()
sdaInterconnect.addHardDriver(dut.io_i2c_sda_write)
sdaInterconnect.addHardReader(dut.io_i2c_sda_read)
dut.io_config_samplingClockDivider <= 3
dut.io_config_timeout <= 25*10-1
dut.io_config_tsuDat <= 4
softMaster = I2cSoftMaster(sclInterconnect.newSoftConnection(), sdaInterconnect.newSoftConnection(), 2500000,dut.clk)
masterCmds = []
slaveCmds = []
slaveRsps = []
masterRsps = []
masterCmds.append(10)
for frameId in range(50):
masterCmds.append("start")
slaveCmds.append("start")
while True:
for bitId in range(randInt(1,10)):
masterValue = random.uniform(0,1) > 0.5
slaveValue = random.uniform(0,1) > 0.5
slaveEnable = random.uniform(0,1) > 0.5
value = masterValue and (slaveValue or not slaveEnable)
masterCmds.append(masterValue)
slaveRsps.append(slaveValue if slaveEnable else "Z")
slaveCmds.append("drive")
slaveCmds.append(value)
masterRsps.append(value)
if random.uniform(0,1) < 0.1:
slaveCmds.append("drive")
slaveRsps.append(random.uniform(0,1) > 0.5)
masterCmds.append(20)
masterCmds.append("drop")
masterCmds.append(randInt(1,10))
slaveCmds.append("stop")
break
slaveRsps.append("Z")
if random.uniform(0,1) < 0.5:
masterCmds.append("stop")
slaveCmds.append("drive")
slaveCmds.append(False)
slaveCmds.append("stop")
masterCmds.append(randInt(1,10))
break
masterCmds.append("restart")
slaveCmds.append("drive")
slaveCmds.append(True)
slaveCmds.append("start")
masterThread = fork(i2cMasterThread(softMaster, masterCmds,masterRsps))
slaveThread = fork(i2cSlaveThread(Flow(dut,"io_cmd"),Flow(dut,"io_rsp"),slaveCmds,slaveRsps, dut.clk))
yield masterThread.join()
def pixelSolverTester(dut):
dut.log.info("Cocotb test boot")
speedBench = True
# Create Agents
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cycleCounter = [0]
cocotb.fork(cycleCounterAgent(dut, cycleCounter))
cmdThread = cocotb.fork(cmdAgent(dut, 1.0 if speedBench else 0.5))
resultArray = [[0 for x in xrange(resX)] for y in xrange(resY)]
rspThread = cocotb.fork(
rspAgent(dut, resultArray, 1.0 if speedBench else 0.5))
# Wait everybody finish its job
yield cmdThread.join()
yield rspThread.join()
# Flush the mandelbrot into a text file
uutString = reduce(lambda a, b: a + "\n" + b,
[str(e) for e in resultArray])
uutFile = open('mandelbrot.uut', 'w')
uutFile.write(uutString)
uutFile.flush()
uutFile.close()
# Count how many iteration were done
iterationCount = 0
for y in xrange(resY):
for x in xrange(resX):
iterationCount += resultArray[y][x] + 1
print("Done in %d cycles => %f iteration/cycle" %
(cycleCounter[0], 1.0 * iterationCount / cycleCounter[0]))
# Display the mandelbrot picture in a GUI
from Tkinter import Tk, Canvas, PhotoImage
zoomFactor = 4
pictureWidth, pictureHeight = resX * zoomFactor, resY * zoomFactor
window = Tk()
canvas = Canvas(window,
width=pictureWidth,
height=pictureHeight,
bg="#000000")
canvas.pack()
img = PhotoImage(width=pictureWidth, height=pictureHeight)
canvas.create_image((pictureWidth / 2, pictureHeight / 2),
image=img,
state="normal")
for y in xrange(resY):
for x in xrange(resX):
r, g, b = 0, 0, 0
r = resultArray[y][x] << 4
for zy in xrange(zoomFactor):
for zx in xrange(zoomFactor):
img.put("#%02x%02x%02x" % (r, g, b),
(x * zoomFactor + zx, y * zoomFactor + zy))
window.mainloop()
# Check differences with the reference image
refFile = open('mandelbrot.ref', 'r')
refString = refFile.read()
if refString != uutString:
raise TestFailure(
"FAIL because of picture missmatch, see mandelbrot.ref vs mandelbrot.uut"
)
def test1(dut):
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset,100000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(2000 * 2.5e6))
sclInterconnect = OpenDrainInterconnect()
sclInterconnect.addHardDriver(dut.io_i2c_scl_write)
sclInterconnect.addHardReader(dut.io_i2c_scl_read)
sdaInterconnect = OpenDrainInterconnect()
sdaInterconnect.addHardDriver(dut.io_i2c_sda_write)
sdaInterconnect.addHardReader(dut.io_i2c_sda_read)
softMaster = I2cSoftMaster(sclInterconnect.newSoftConnection(), sdaInterconnect.newSoftConnection(), 2500000,dut.clk)
apb = Apb3(dut, "io_apb", dut.clk)
apb.idle()
@coroutine
def txData(valid = False, enable = False, value = 0xFF, repeat = False, disableOnConflict = False):
yield apb.write(0, (valid << 8) | (enable << 9) | (value << 0) | (repeat << 10) | (disableOnConflict << 11))
@coroutine
def txAck(valid=False, enable=False, value=0x1, repeat=False, disableOnConflict=False):
yield apb.write(4, (valid << 8) | (enable << 9) | (value << 0) | (repeat << 10) | (disableOnConflict << 11))
@coroutine
def rxDataConfig(listen = False):
yield apb.write(8, listen << 9)
@coroutine
def rxAckConfig(listen = False):
yield apb.write(12, listen << 9)
@coroutine
def rxDataValue(expected):
yield apb.readAssertMasked(8, 0x100 | expected, 0x1FF)
@coroutine
def rxAckValue(expected):
yield apb.readAssertMasked(12, 0x100 | expected, 0x101)
@coroutine
def rxDataNotValid():
yield apb.readAssertMasked(8, 0, 0x100)
@coroutine
def rxAckNotValid():
yield apb.readAssertMasked(12, 0, 0x100)
@coroutine
def addressFilter(index, enable = False, is10Bits = False, value = 0):
yield apb.write(136+index*4, (enable << 15) | (is10Bits << 14) | (value << 0))
@coroutine
def addressFilterHits(value):
yield apb.readAssertMasked(128, value, 0xFFFFFFFF)
@coroutine
def idle():
yield txData(valid = True, repeat = True)
yield txAck(valid=True, repeat=True)
yield rxDataConfig(listen=False)
yield rxAckConfig(listen=False)
buffer = [0]
yield apb.write(40, 3) #samplingClockDivider
yield apb.write(44, 25*20-1) #timeout
yield apb.write(48, 4) #tsuDat
#Check idle controller
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xAA, 0xAA)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x55, 0x55)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# Check simple txData
yield idle()
yield txData(valid = True, enable = True, value = 0x0F)
yield rxDataConfig(listen=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xAA, 0x0A)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield rxDataValue(0x0A)
yield rxDataNotValid();
yield softMaster.wait(5)
# Check simple txAck
yield idle()
yield txAck(valid=True, enable=True, value=False)
yield rxAckConfig(listen=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xFF, 0xFF)
yield softMaster.sendBitCheck(True, False)
yield rxAckValue(False)
yield txAck(valid=True, enable=True, value=True)
yield softMaster.sendByteCheck(0x00, 0x00)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield rxAckValue(True)
yield softMaster.wait(5)
# Check explicit idle controller
yield idle()
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xAA, 0xAA)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x55, 0x55)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# Check tx clock stretching
yield idle()
yield txData(valid=False)
yield txAck(valid=False)
yield softMaster.wait(2)
yield softMaster.sendStart()
txThread = fork(softMaster.sendByteCheck(0xAA, 0x0A))
yield softMaster.wait(10)
yield txData(valid = True, enable = True, value = 0x0F)
yield txThread.join()
txThread = fork(softMaster.sendBitCheck(True, False))
yield softMaster.wait(10)
yield txAck(valid=True, enable=True, value=False)
yield txThread.join()
txThread = fork(softMaster.sendByteCheck(0x55, 0x50))
yield softMaster.wait(10)
yield txData(valid = True, enable = True, value = 0xF0)
yield txThread.join()
txThread = fork(softMaster.sendBitCheck(True, False))
yield softMaster.wait(10)
yield txAck(valid=True, enable=True, value=False)
yield txThread.join()
yield txData(valid = True, enable = True, value = 0x8F)
yield txAck(valid=True, enable=True, value=True)
yield softMaster.sendByteCheck(0xF3, 0x83)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# Check rxData clock streching
yield idle()
yield rxDataConfig(listen=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x11, 0x11)
yield softMaster.sendBitCheck(False, False)
txThread = fork(softMaster.sendByteCheck(0x22, 0x22))
yield softMaster.wait(16)
yield rxDataValue(0x11)
yield txThread.join()
yield rxDataValue(0x22)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# Check rxAck clock streching
yield idle()
yield rxAckConfig(listen=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x11, 0x11)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x22, 0x22)
txThread = fork(softMaster.sendBitCheck(True, True))
yield softMaster.wait(16)
yield rxAckValue(False)
yield txThread.join()
yield rxAckValue(True)
yield softMaster.sendStop()
yield softMaster.wait(5)
#check txData repeat
yield idle()
yield txData(valid = True, enable = True, value = 0x0F,repeat = True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x33, 0x03)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x44, 0x04)
yield softMaster.sendBitCheck(False, False)
yield softMaster.sendByteCheck(0x55, 0x05)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
# check txAck repeat
yield idle()
yield txAck(valid=True, enable=True, value=0x0, repeat=True)
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x33, 0x33)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendByteCheck(0x44, 0x44)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendByteCheck(0x55, 0x55)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendStop()
yield softMaster.wait(5)
#Check address filter
yield idle()
yield addressFilter(index = 2, enable = True, is10Bits = False, value = 0x63)
yield addressFilter(index = 1, enable = True, is10Bits = True, value = 0x123)
for i in range(2):
#7bits
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x63*2, 0x63*2)
t = fork(softMaster.sendBitCheck(True, False))
yield softMaster.wait(5)
yield addressFilterHits(1 << 2)
yield txData(valid=True, enable=True, value=0xF0)
yield txAck(valid=True, enable=True, value=False)
yield t.join()
yield softMaster.sendByteCheck(0x44, 0x40)
yield txAck(valid=True, repeat=True)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
#10bits
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xF3,0xF3)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendByteCheck(0x23,0x23)
t = fork(softMaster.sendBitCheck(True, False))
yield softMaster.wait(5)
yield addressFilterHits(1 << 1)
yield txData(valid=True, enable=True, value=0xF0)
yield txAck(valid=True, enable=True, value=False)
yield t.join()
yield softMaster.sendByteCheck(0x44, 0x40)
yield txAck(valid=True, repeat=True)
yield softMaster.sendBitCheck(True, True)
yield softMaster.sendStop()
yield softMaster.wait(5)
#10bits no trigger
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0xF3,0xF3)
yield softMaster.sendBitCheck(True, False)
yield softMaster.sendByteCheck(0x54,0x54)
yield softMaster.sendBitCheck(True, True)
yield addressFilterHits(0 << 1)
yield softMaster.sendStop()
yield softMaster.wait(5)
#7bits no trigger
yield softMaster.wait(2)
yield softMaster.sendStart()
yield softMaster.sendByteCheck(0x13,0x13)
yield softMaster.sendBitCheck(True, True)
yield addressFilterHits(0 << 1)
yield softMaster.sendStop()
yield softMaster.wait(5)
def test1(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*2000)
axiMasters = [Axi4(dut, "axiMasters_" + str(i)) for i in range(2)]
axiSlaves = [Axi4(dut, "axiSlaves_" + str(i)) for i in range(2)]
axiReadOnlyMasters = [Axi4ReadOnly(dut, "axiReadOnlyMasters_" + str(i)) for i in range(2)]
axiReadOnlySlaves = [Axi4ReadOnly(dut, "axiReadOnlySlaves_" + str(i)) for i in range(2)]
axiWriteOnlyMasters = [Axi4WriteOnly(dut, "axiWriteOnlyMasters_" + str(i)) for i in range(2)]
axiWriteOnlySlaves = [Axi4WriteOnly(dut, "axiWriteOnlySlaves_" + str(i)) for i in range(2)]
axiSharedMasters = [Axi4Shared(dut, "axiSharedMasters_" + str(i)) for i in range(2)]
axiSharedSlaves = [Axi4Shared(dut, "axiSharedSlaves_" + str(i)) for i in range(2)]
# Instanciate master sides
for idx,axiMaster in enumerate(axiMasters):
WriteOnlyMasterDriver("Axi4WriteMasterDriver" + str(idx),phaseManager,0 + idx * 4, axiMaster, dut).createInfrastructure()
ReadOnlyMasterDriver("Axi4ReadMasterDriver" + str(idx),phaseManager,0 + idx * 4, axiMaster, dut).createInfrastructure()
ReadOnlyMasterMonitor("Axi4ReadMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure()
WriteOnlyMasterMonitor("Axi4WriteMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure()
for idx,axiMaster in enumerate(axiReadOnlyMasters):
ReadOnlyMasterDriver("ReadOnlyMasterDriver" + str(idx),phaseManager,4 + idx * 4, axiMaster, dut).createInfrastructure()
ReadOnlyMasterMonitor("ReadOnlyMasterMonitor" + str(idx),phaseManager,axiMaster,dut).createInfrastructure()
for idx,axiMaster in enumerate(axiWriteOnlyMasters):
WriteOnlyMasterDriver("WriteOnlyMasterDriver" + str(idx),phaseManager,8 + idx * 4, axiMaster, dut).createInfrastructure()
WriteOnlyMasterMonitor("WriteOnlyMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure()
for idx,axiMaster in enumerate(axiSharedMasters):
SharedMasterDriver("SharedMasterDriver" + str(idx),phaseManager,12 + idx * 4, axiMaster, dut).createInfrastructure()
SharedMasterMonitor("SharedMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure()
for idx,axiSlave in enumerate(axiSlaves):
WriteOnlySlaveDriver(axiSlave,0x0000 + idx*0x0800,0x0800, dut).createInfrastructure()
ReadOnlySlaveDriver(axiSlave,0x0000 + idx*0x0800,0x0800, dut).createInfrastructure()
WriteDataMonitor("Axi4DataSlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure()
for idx,axiSlave in enumerate(axiReadOnlySlaves):
ReadOnlySlaveDriver(axiSlave,0x2000 + idx*0x0800,0x0800, dut).createInfrastructure()
for idx,axiSlave in enumerate(axiWriteOnlySlaves):
WriteOnlySlaveDriver(axiSlave,0x3000 + idx*0x0800,0x0800, dut).createInfrastructure()
WriteDataMonitor("WriteOnlySlaveMonitor" + str(idx),phaseManager,axiSlave,dut).createInfrastructure()
for idx,axiSlave in enumerate(axiSharedSlaves):
SharedSlaveDriver(axiSlave,0x1000 + idx*0x0800,0x0800, dut).createInfrastructure()
SharedDataMonitor("SharedSlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure()
# cocotb.log.error("miaou")
# Run until completion
yield phaseManager.run()
# yield Timer(1000*6000)
dut.log.info("Cocotb test done")
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
cocotb.fork(
ClockDomainAsyncResetCustom(3300, dut.clk0, dut.serdesClk0,
dut.serdesClk90, dut.rst0))
cocotb.fork(simulationSpeedPrinter(dut.clk0))
bmbs = [Bmb(dut, "system_io_ports_" + str(x)) for x in range(1)]
tester = BmbMemoryTester(bmbs, 64 * 1024, 8, 32, dut.clk0, dut.rst0, True)
@cocotb.coroutine
def delay():
yield RisingEdge(dut.clk0)
ctrlApb = Apb3(dut, "system_io_ctrlApb", dut.clk0)
phyApb = Apb3(dut, "system_io_phyApb", dut.clk0)
@cocotb.coroutine
def apbWrite(address, data):
yield ctrlApb.write(address, data)
yield apbWrite(0x0, 0x20001)
yield apbWrite(0x4, 0x2)
yield apbWrite(0x10, 0x491)
yield apbWrite(0x20, 0x1170205)
yield apbWrite(0x24, 0x2)
yield apbWrite(0x28, 0x2030102)
yield apbWrite(0x30, 0x5)
yield apbWrite(0x34, 0x103)
yield apbWrite(0x110, 0x0)
yield apbWrite(0x110, 0x1)
yield apbWrite(0x110, 0x3)
yield apbWrite(0x10c, 0x2)
yield apbWrite(0x108, 0x200)
yield apbWrite(0x104, 0x0)
yield apbWrite(0x100, 0x0)
yield apbWrite(0x10c, 0x3)
yield apbWrite(0x108, 0x0)
yield apbWrite(0x104, 0x0)
yield apbWrite(0x100, 0x0)
yield apbWrite(0x10c, 0x1)
yield apbWrite(0x108, 0x44)
yield apbWrite(0x104, 0x0)
yield apbWrite(0x100, 0x0)
yield apbWrite(0x10c, 0x0)
yield apbWrite(0x108, 0x310)
yield apbWrite(0x104, 0x0)
yield apbWrite(0x100, 0x0)
yield apbWrite(0x10c, 0x0)
yield apbWrite(0x108, 0x400)
yield apbWrite(0x104, 0xc)
yield apbWrite(0x100, 0x0)
# yield ctrlApb.write(0x000, 0x00) #phase command = 0
# yield ctrlApb.write(0x110, 0x00) #reset
# yield ctrlApb.delay(10)
# yield ctrlApb.write(0x110, 0x01) #!reset
# yield ctrlApb.delay(10)
# yield ctrlApb.write(0x110, 0x03) #cke
# yield ctrlApb.delay(10)
#
#
# @cocotb.coroutine
# def command(cmd, bank, address):
# yield ctrlApb.write(0x10C, bank)
# yield ctrlApb.write(0x108, address)
# yield ctrlApb.write(0x104, cmd)
# yield ctrlApb.write(0x100, 0)
# yield ctrlApb.delay(10)
#
# CKE = 1 << 0
# CSn = 1 << 1
# RASn = 1 << 2
# CASn = 1 << 3
# WEn = 1 << 4
#
# PRE = CKE | CASn
# REF = CKE | WEn
# MOD = CKE
# ZQCL = CKE | RASn | CASn
#
# CL = 2 # 5
#
#
# yield command(MOD, 2, 0)
# yield command(MOD, 3, 0)
# yield command(MOD, 1, 0)
# yield command(MOD, 0, (1 << 9) | 0x100 | ((CL & 1) << 2) | ((CL & 0xE) << 3)) #DDL reset
# yield command(ZQCL, 0, 0x400)
# yield ctrlApb.delay(1000)
delay()
tester.run = True
while True:
yield Timer(0x1000000)