from common.genesis_wrapper import GenesisWrapper, default_type_map
from common.generator_interface import GeneratorInterface
interface = GeneratorInterface()\
.register("width", int, 16)\
.register("num_tracks", int, 10)
simple_cb_wrapper = GenesisWrapper(
interface,
"simple_cb",
["simple_cb/genesis/simple_cb.vp"],
type_map=default_type_map)
if __name__ == "__main__":
# These functions are unit tested directly, so no need to cover them
simple_cb_wrapper.main() # pragma: no cover
`data_width`: width of an entry in the memory
`data_depth`: number of entries in the memory
Example usage:
>>> memory_core = memory_core_wrapper.generator()(
data_width=16, data_depth=1024)
"""
interface = GeneratorInterface()\
.register("data_width", int, 16)\
.register("data_depth", int, 1024)
memory_core_wrapper = GenesisWrapper(
interface, "memory_core", ["memory_core/genesis/input_sr.vp",
"memory_core/genesis/output_sr.vp",
"memory_core/genesis/linebuffer_control.vp",
"memory_core/genesis/fifo_control.vp",
"memory_core/genesis/mem.vp",
"memory_core/genesis/memory_core.vp"],
type_map={"clk_in": m.In(m.Clock),
"reset": m.In(m.AsyncReset),
"config_en": m.In(m.Enable)})
param_mapping = {"data_width": "dwidth", "data_depth": "ddepth"}
if __name__ == "__main__":
"""
This program generates the verilog for the memory core and parses it into a
Magma circuit. The circuit declaration is printed at the end of the
program.
"""
# These functions are unit tested directly, so no need to cover them
memory_core_wrapper.main(param_mapping=param_mapping) # pragma: no cover
.register("reg_cnt", int, 1)
type_map = {
"clk": magma.In(magma.Clock),
"rst_n": magma.In(magma.AsyncReset),
}
pe_core_wrapper = GenesisWrapper(
interface,
"test_pe", [
"pe_core/genesis/test_pe_red.svp", "pe_core/genesis/test_pe_dual.vpf",
"pe_core/genesis/test_pe_comp.svp",
"pe_core/genesis/test_pe_comp_dual.svp",
"pe_core/genesis/test_cmpr.svp", "pe_core/genesis/test_pe.svp",
"pe_core/genesis/test_mult_add.svp",
"pe_core/genesis/test_full_add.svp", "pe_core/genesis/test_lut.svp",
"pe_core/genesis/test_opt_reg.svp",
"pe_core/genesis/test_simple_shift.svp",
"pe_core/genesis/test_shifter.svp",
"pe_core/genesis/test_debug_reg.svp",
"pe_core/genesis/test_opt_reg_file.svp"
],
system_verilog=True,
type_map=type_map)
if __name__ == "__main__":
"""
This program generates the verilog for the pe and parses it into a
Magma circuit. The circuit declaration is printed at the end of the
program.
"""
import pytest
import inspect
import random
import magma as m
from common.genesis_wrapper import GenesisWrapper
from common.generator_interface import GeneratorInterface
TOP = "test_run_genesis"
INFILES = ["test_common/test_run_genesis.vp"]
PARAMS = {
"width": 16,
}
INTERFACE = GeneratorInterface()\
.register("width", int, 32)
WRAPPER = GenesisWrapper(INTERFACE, TOP, INFILES)
@pytest.mark.parametrize("mode", ["declare", "define"])
def test_generator(mode):
def _foo(*args, **kwargs):
pass
generator = WRAPPER.generator(mode=mode)
assert inspect.isfunction(generator)
assert inspect.signature(generator) == inspect.signature(_foo)
# Check that passing non-kwargs fails.
try:
generator(0)
assert False
except NotImplementedError as e:
pass
from common.genesis_wrapper import GenesisWrapper, default_type_map
from common.generator_interface import GeneratorInterface
import magma as m
interface = GeneratorInterface()\
.register("width", int, 16)\
.register("num_tracks", int, 10)\
.register("feedthrough_outputs", str, "1" * 10)\
.register("has_constant", int, 0)\
.register("default_value", int, 0)
cb_wrapper = GenesisWrapper(interface, "cb", ["cb/genesis/cb.vp"],
type_map=default_type_map)
"""
This program generates the verilog for the connect box and parses it into a
Magma circuit. The circuit declaration is printed at the end of the program.
"""
if __name__ == "__main__":
# These functions are unit tested directly, so no need to cover them
cb_wrapper.main() # pragma: no cover
.register("cfg_addr_width", int, 32)\
.register("cfg_op_width", int, 5)
type_map = {
"clk_in": magma.In(magma.Clock),
"clk_out": magma.Out(magma.Clock),
"tck": magma.In(magma.Clock),
"reset_in": magma.In(magma.AsyncReset),
"reset_out": magma.Out(magma.AsyncReset),
"trst_n": magma.In(magma.AsyncReset),
}
gc_wrapper = GenesisWrapper(
interface,
"global_controller", [
"global_controller/genesis/global_controller.vp",
"global_controller/genesis/jtag.vp",
"global_controller/genesis/tap.vp",
"global_controller/genesis/flop.vp",
"global_controller/genesis/cfg_and_dbg.vp"
],
type_map=type_map)
if __name__ == "__main__":
"""
This program generates the verilog for the global controller and parses it
into a Magma circuit. The circuit declaration is printed at the end of the
program.
"""
# These functions are unit tested directly, so no need to cover them
gc_wrapper.main() # pragma: no cover
`tile_id_offset`: ID we begin counting from to assign
ids to each io1bit tile. Will probably get
rid of this once we develop configuration manager
Example usage:
>>> pad_frame = pad_frame_wrapper.generator()(
config_data_width=32, config_addr_width=32,
num_ios_per_group=16, num_groups_per_side=1,
tile_id_offset=400)
"""
interface = GeneratorInterface()\
.register("num_ios_per_group", int, 16)\
.register("num_groups_per_side", int, 1)\
.register("config_addr_width", int, 32)\
.register("config_data_width", int, 32)\
.register("tile_id_offset", int, 400)
pad_frame_wrapper = GenesisWrapper(interface, "pad_frame", [
"pad_frame/genesis/pad_frame.vp", "pad_frame/genesis/io_group.vp",
"pad_frame/genesis/io1bit.vp", "pad_frame/genesis/fixed_io.vp"
])
if __name__ == "__main__":
"""
This program generates the verilog for the pad frame and parses it into a
Magma circuit. The circuit declaration is printed at the end of the
program.
"""
# These functions are unit tested directly, so no need to cover them
pad_frame_wrapper.main() # pragma: no cover