def gen_constraints(self):
cons = []
cons.append(PortConstraint('FIXED_IO_ddr_vrp', 'FIXED_IO_ddr_vrp'))
cons.append(PortConstraint('FIXED_IO_ddr_vrn', 'FIXED_IO_ddr_vrn'))
cons.append(PortConstraint('DDR_we_n', 'DDR_we_n'))
cons.append(PortConstraint('DDR_RAS_n', 'DDR_RAS_n'))
cons.append(PortConstraint('DDR_ODT', 'DDR_ODT'))
cons.append(PortConstraint('DDR_reset_n', 'DDR_reset_n'))
cons.append(
PortConstraint('DDR_DQS_p',
'DDR_DQS_p',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('DDR_DQS_n',
'DDR_DQS_n',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('DDR_DQ',
'DDR_DQ',
port_index=list(range(32)),
iogroup_index=list(range(32))))
cons.append(
PortConstraint('DDR_DM',
'DDR_DM',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(PortConstraint('DDR_CS_n', 'DDR_CS_n'))
cons.append(PortConstraint('DDR_CKE', 'DDR_CKE'))
cons.append(PortConstraint('DDR_Ck_p', 'DDR_Ck_p'))
cons.append(PortConstraint('DDR_Ck_n', 'DDR_Ck_n'))
cons.append(PortConstraint('DDR_CAS_n', 'DDR_CAS_n'))
cons.append(
PortConstraint('DDR_ba',
'DDR_ba',
port_index=list(range(3)),
iogroup_index=list(range(3))))
cons.append(
PortConstraint('DDR_Addr',
'DDR_Addr',
port_index=list(range(15)),
iogroup_index=list(range(15))))
cons.append(PortConstraint('FIXED_IO_ps_porb', 'FIXED_IO_ps_porb'))
cons.append(PortConstraint('FIXED_IO_ps_srstb', 'FIXED_IO_ps_srstb'))
cons.append(PortConstraint('FIXED_IO_ps_clk', 'FIXED_IO_ps_clk'))
cons.append(PortConstraint('ADC_CLK_IN_P', 'ADC_CLK_IN_P'))
cons.append(
ClockConstraint('ADC_CLK_IN_P',
'ADC_CLK_IN_P',
period=8.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=4.0))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins red_pitaya_infr_inst/dsp_clk_mmcm_inst/CLKOUT0]',
'-of_objects [get_pins red_pitaya_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]]',
'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins red_pitaya_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]]',
'-of_objects [get_pins red_pitaya_infr_inst/dsp_clk_mmcm_inst/CLKOUT0]',
'asynchronous'))
return cons
def gen_constraints(self):
num = self.infrastructure_id
cons = []
cons.append(
PortConstraint('ref_clk_p%d' % num, 'eth_clk_p',
iogroup_index=num))
cons.append(
PortConstraint('ref_clk_n%d' % num, 'eth_clk_n',
iogroup_index=num))
cons.append(
PortConstraint('mgt_tx_p%d' % self.port,
'mgt_tx_p',
iogroup_index=self.port))
cons.append(
PortConstraint('mgt_tx_n%d' % self.port,
'mgt_tx_n',
iogroup_index=self.port))
cons.append(
PortConstraint('mgt_rx_p%d' % self.port,
'mgt_rx_p',
iogroup_index=self.port))
cons.append(
PortConstraint('mgt_rx_n%d' % self.port,
'mgt_rx_n',
iogroup_index=self.port))
cons.append(
ClockConstraint('ref_clk_p%d' % num,
name='ethclk%d' % num,
freq=156.25))
cons.append(
RawConstraint(
'set_false_path -from [get_pins {tengbaser_infra%d_inst/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_shared_clock_reset_block/reset_pulse_reg[0]/C}] -to [get_pins {tengbaser_infra%d_inst/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_shared_clock_reset_block/gttxreset_txusrclk2_sync_i/sync1_r_reg*/PRE}]'
% (num, num)))
# make the ethernet core clock async relative to whatever the user is using as user_clk
# Find the clock of *clk_counter* to determine what source user_clk comes from. This is fragile.
if self.platform.name == 'snap':
cons.append(
PortConstraint('tx_disable%d' % self.port,
'sfp_disable',
iogroup_index=self.port))
cons.append(
RawConstraint(
'set_clock_groups -name asyncclocks_eth%d -asynchronous -group [get_clocks -include_generated_clocks sys_clk_p_CLK] -group [get_clocks -include_generated_clocks ethclk%d]'
% (num, num)))
cons.append(
RawConstraint(
'set_clock_groups -name asyncclocks_eth%d_usr_clk -asynchronous -group [get_clocks -of_objects [get_cells -hierarchical -filter {name=~*clk_counter*}]] -group [get_clocks -include_generated_clocks ethclk%d]'
% (num, num)))
else:
cons.append(
RawConstraint(
'set_clock_groups -name asyncclocks_eth%d -asynchronous -group [get_clocks -include_generated_clocks sys_clk_in_CLK] -group [get_clocks -include_generated_clocks ethclk%d]'
% (num, num)))
cons.append(
RawConstraint(
'set_clock_groups -name asyncclocks_eth%d_usr_clk -asynchronous -group [get_clocks -of_objects [get_cells -hierarchical -filter {name=~*clk_counter*}]] -group [get_clocks -include_generated_clocks ethclk%d]'
% (num, num)))
return cons
def gen_constraints(self):
cons = []
cons.append(PortConstraint('ext_sys_rst_n', 'ext_sys_rst_n'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_adr_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_aor_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_bor_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_cor_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_dor_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[0]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[1]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[2]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[3]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[4]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[5]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[6]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[7]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[8]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_a_p[9]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[0]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[1]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[2]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[3]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[4]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[5]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[6]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[7]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[8]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_b_p[9]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[0]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[1]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[2]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[3]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[4]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[5]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[6]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[7]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[8]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_c_p[9]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[0]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[1]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[2]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[3]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[4]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[5]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[6]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[7]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[8]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip1_d_p[9]}]'))
clkconst = ClockConstraint('adc_5g_chip1_adr_p', 'adc_5g_chip1_adr_p', freq=self.f_sample/2/self.work_mode)
cons.append(clkconst)
if self.chips_num ==1:
cons.append(PortConstraint('adc_5g_chip1_adr_p', 'adc_5g_chip%d_adr_p'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_aor_p', 'adc_5g_chip%d_aor_p'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_bor_p', 'adc_5g_chip%d_bor_p'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_cor_p', 'adc_5g_chip%d_cor_p'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_dor_p', 'adc_5g_chip%d_dor_p'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_a_p' , 'adc_5g_chip%d_a_p'%self.fmc_port , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip1_b_p' , 'adc_5g_chip%d_b_p'%self.fmc_port , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip1_c_p' , 'adc_5g_chip%d_c_p'%self.fmc_port , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip1_d_p' , 'adc_5g_chip%d_d_p'%self.fmc_port , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip1_sclk', 'adc_5g_chip%d_sclk'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_sen' , 'adc_5g_chip%d_sen'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_rst' , 'adc_5g_chip%d_rst'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_mosi', 'adc_5g_chip%d_mosi'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_miso', 'adc_5g_chip%d_miso'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_sync', 'adc_5g_chip%d_sync'%self.fmc_port))
cons.append(PortConstraint('adc_5g_chip1_sync_dir', 'adc_5g_chip%d_sync_dir'%self.fmc_port))
else:#work in synchronization mode
cons.append(PortConstraint('adc_5g_chip1_adr_p', 'adc_5g_chip1_adr_p'))
cons.append(PortConstraint('adc_5g_chip1_aor_p', 'adc_5g_chip1_aor_p'))
cons.append(PortConstraint('adc_5g_chip1_bor_p', 'adc_5g_chip1_bor_p'))
cons.append(PortConstraint('adc_5g_chip1_cor_p', 'adc_5g_chip1_cor_p'))
cons.append(PortConstraint('adc_5g_chip1_dor_p', 'adc_5g_chip1_dor_p'))
cons.append(PortConstraint('adc_5g_chip1_a_p' , 'adc_5g_chip1_a_p' , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip1_b_p' , 'adc_5g_chip1_b_p' , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip1_c_p' , 'adc_5g_chip1_c_p' , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip1_d_p' , 'adc_5g_chip1_d_p' , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip1_sclk', 'adc_5g_chip1_sclk'))
cons.append(PortConstraint('adc_5g_chip1_sen' , 'adc_5g_chip1_sen'))
cons.append(PortConstraint('adc_5g_chip1_rst' , 'adc_5g_chip1_rst'))
cons.append(PortConstraint('adc_5g_chip1_mosi', 'adc_5g_chip1_mosi'))
cons.append(PortConstraint('adc_5g_chip1_miso', 'adc_5g_chip1_miso'))
cons.append(PortConstraint('adc_5g_chip1_sync', 'adc_5g_chip1_sync'))
cons.append(PortConstraint('adc_5g_chip1_sync_dir', 'adc_5g_chip1_sync_dir'))
cons.append(PortConstraint('adc_5g_chip2_adr_p', 'adc_5g_chip2_adr_p'))
cons.append(PortConstraint('adc_5g_chip2_aor_p', 'adc_5g_chip2_aor_p'))
cons.append(PortConstraint('adc_5g_chip2_bor_p', 'adc_5g_chip2_bor_p'))
cons.append(PortConstraint('adc_5g_chip2_cor_p', 'adc_5g_chip2_cor_p'))
cons.append(PortConstraint('adc_5g_chip2_dor_p', 'adc_5g_chip2_dor_p'))
cons.append(PortConstraint('adc_5g_chip2_a_p' , 'adc_5g_chip2_a_p' , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip2_b_p' , 'adc_5g_chip2_b_p' , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip2_c_p' , 'adc_5g_chip2_c_p' , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip2_d_p' , 'adc_5g_chip2_d_p' , port_index=list(range(10)), iogroup_index=list(range(10))))
cons.append(PortConstraint('adc_5g_chip2_sclk', 'adc_5g_chip2_sclk'))
cons.append(PortConstraint('adc_5g_chip2_sen' , 'adc_5g_chip2_sen'))
cons.append(PortConstraint('adc_5g_chip2_rst' , 'adc_5g_chip2_rst'))
cons.append(PortConstraint('adc_5g_chip2_mosi', 'adc_5g_chip2_mosi'))
cons.append(PortConstraint('adc_5g_chip2_miso', 'adc_5g_chip2_miso'))
cons.append(PortConstraint('adc_5g_chip2_sync', 'adc_5g_chip2_sync'))
cons.append(PortConstraint('adc_5g_chip2_sync_dir', 'adc_5g_chip2_sync_dir'))
cons.append(PortConstraint(self.fullname+'_trig_dir', 'adc_5g_chip2_trig_dir'))
cons.append(PortConstraint(self.fullname+'_trig_ext', 'adc_5g_chip2_trig_ext'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_adr_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_aor_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_bor_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_cor_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_dor_p}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[1]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[2]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[3]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[4]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[5]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[6]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[7]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[8]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_a_p[9]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[0]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[1]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[2]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[3]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[4]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[5]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[6]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[7]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[8]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_b_p[9]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[0]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[1]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[2]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[3]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[4]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[5]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[6]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[7]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[8]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_c_p[9]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[0]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[1]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[2]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[3]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[4]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[5]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[6]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[7]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[8]}]'))
cons.append(RawConstraint('set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_5g_chip2_d_p[9]}]'))
clkconst = ClockConstraint('adc_5g_chip2_adr_p', 'adc_5g_chip2_adr_p', freq=self.f_sample/2/self.work_mode)
cons.append(clkconst)
return cons
def gen_constraints(self):
cons = []
# ADC SPI interface
cons.append(PortConstraint('adc0_adc3wire_csn1', 'adc_csn', iogroup_index=0))
cons.append(PortConstraint('adc0_adc3wire_csn2', 'adc_csn', iogroup_index=1))
cons.append(PortConstraint('adc0_adc3wire_csn3', 'adc_csn', iogroup_index=2))
cons.append(PortConstraint('adc0_adc3wire_sdata', 'adc_sdata', port_index=list(range(3)), iogroup_index=list(range(3))))
cons.append(PortConstraint('adc0_adc3wire_sclk', 'adc_sclk', port_index=list(range(3)), iogroup_index=list(range(3))))
cons.append(PortConstraint('adc16_clk_line_p', 'adc_lclkp', iogroup_index=0))
cons.append(PortConstraint('adc16_clk_line_n', 'adc_lclkn', iogroup_index=0))
# in 4 channel mode, the adc controller demuxes each a-b pair to make a stream
# in 2 channel mode, the demux order should be a[2*n],a[2*n+1],b[2*n],b[2*n+1] for n in range(2)
# in 1 channel mode, the demux order should be a[0],a[2],b[0],b[2],a[1],a[3],b[1],b[3]
# In the board description file, adcX_out is a 16 element vector with a_p[0], a_n[0], b_p[0], b_n[0], a_p[1], ... b_n[15]
# This is now configured dynamically in the gateware
#if self.n_inputs == 4:
# ap_index = [0, 4, 8, 12]
# an_index = [1, 5, 9, 13]
# bp_index = [2, 6, 10, 14]
# bn_index = [3, 7, 11, 15]
#elif self.n_inputs == 2:
# ap_index = [0, 2, 8, 10]
# an_index = [1, 3, 9, 11]
# bp_index = [4, 6, 12, 14]
# bn_index = [5, 7, 13, 15]
#elif self.n_inputs == 1:
# ap_index = [0, 2, 4, 6]
# an_index = [1, 3, 5, 7]
# bp_index = [8, 10, 12, 14]
# bn_index = [9, 11, 13, 15]
#
ap_index = [0, 4, 8, 12]
an_index = [1, 5, 9, 13]
bp_index = [2, 6, 10, 14]
bn_index = [3, 7, 11, 15]
cons.append(PortConstraint('adc16_ser_a_p', 'adc0_out', port_index=list(range(4)), iogroup_index=ap_index))
cons.append(PortConstraint('adc16_ser_a_n', 'adc0_out', port_index=list(range(4)), iogroup_index=an_index))
cons.append(PortConstraint('adc16_ser_b_p', 'adc0_out', port_index=list(range(4)), iogroup_index=bp_index))
cons.append(PortConstraint('adc16_ser_b_n', 'adc0_out', port_index=list(range(4)), iogroup_index=bn_index))
cons.append(PortConstraint('adc16_ser_a_p', 'adc1_out', port_index=list(range(4,8)), iogroup_index=ap_index))
cons.append(PortConstraint('adc16_ser_a_n', 'adc1_out', port_index=list(range(4,8)), iogroup_index=an_index))
cons.append(PortConstraint('adc16_ser_b_p', 'adc1_out', port_index=list(range(4,8)), iogroup_index=bp_index))
cons.append(PortConstraint('adc16_ser_b_n', 'adc1_out', port_index=list(range(4,8)), iogroup_index=bn_index))
cons.append(PortConstraint('adc16_ser_a_p', 'adc2_out', port_index=list(range(8,12)), iogroup_index=ap_index))
cons.append(PortConstraint('adc16_ser_a_n', 'adc2_out', port_index=list(range(8,12)), iogroup_index=an_index))
cons.append(PortConstraint('adc16_ser_b_p', 'adc2_out', port_index=list(range(8,12)), iogroup_index=bp_index))
cons.append(PortConstraint('adc16_ser_b_n', 'adc2_out', port_index=list(range(8,12)), iogroup_index=bn_index))
if self.i_am_the_first:
cons.append(PortConstraint('clk_sel_a', 'clk_sel_a', port_index=list(range(1)), iogroup_index=list(range(1))))
cons.append(PortConstraint('clk_sel_b', 'clk_sel_b', port_index=list(range(1)), iogroup_index=list(range(1))))
cons.append(PortConstraint('adc_rst_n', 'adc_rst_n', port_index=list(range(3)), iogroup_index=list(range(3))))
cons.append(PortConstraint('adc_pd', 'adc_pd', port_index=list(range(3)), iogroup_index=list(range(3))))
# clock constraint with variable period
clkconst = ClockConstraint('adc16_clk_line_p', name='adc_clk', freq=self.line_clock_freq)
cons.append(clkconst)
cons.append(RawConstraint('set_clock_groups -name async_sysclk_adcclk -asynchronous -group [get_clocks -include_generated_clocks %s] -group [get_clocks -include_generated_clocks sys_clk0_dcm]' % clkconst.name))
cons.append(RawConstraint('set_multicycle_path -from [get_clocks -include_generated_clocks %s] -to [get_clocks -include_generated_clocks sys_clk0_dcm] 3' % clkconst.name))
cons.append(RawConstraint('set_multicycle_path -from [get_clocks -include_generated_clocks %s] -to [get_clocks -include_generated_clocks sys_clk0_dcm] -hold 2' % clkconst.name))
return cons
def gen_constraints(self):
if self.use_diffio:
const = []
const += [
PortConstraint(self.fullname + '_ext_p',
self.io_group + '_p',
port_index=list(range(self.bitwidth)),
iogroup_index=to_int_list(self.bit_index))
]
const += [
PortConstraint(self.fullname + '_ext_n',
self.io_group + '_n',
port_index=list(range(self.bitwidth)),
iogroup_index=to_int_list(self.bit_index))
]
#Constrain the I/O (it is assumed that this I/O is not timing critical and set_false_path is used)
#NB: The set_max_delay and set_min_delay is important as Vivado will report that these signals are not
#constrained without it
if self.io_dir == 'in':
const += [
MaxDelayConstraint(sourcepath='[get_ports {%s_ext_p[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
MaxDelayConstraint(sourcepath='[get_ports {%s_ext_n[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
MinDelayConstraint(sourcepath='[get_ports {%s_ext_p[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
MinDelayConstraint(sourcepath='[get_ports {%s_ext_n[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
FalsePathConstraint(
sourcepath='[get_ports {%s_ext_p[*]}]' % self.fullname)
]
const += [
FalsePathConstraint(
sourcepath='[get_ports {%s_ext_n[*]}]' % self.fullname)
]
elif self.io_dir == 'out':
const += [
MaxDelayConstraint(destpath='[get_ports {%s_ext_p[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
MaxDelayConstraint(destpath='[get_ports {%s_ext_n[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
MinDelayConstraint(destpath='[get_ports {%s_ext_p[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
MinDelayConstraint(destpath='[get_ports {%s_ext_n[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
FalsePathConstraint(destpath='[get_ports {%s_ext_p[*]}]' %
self.fullname)
]
const += [
FalsePathConstraint(destpath='[get_ports {%s_ext_n[*]}]' %
self.fullname)
]
return const
else:
const = []
if self.io_group.find('gpio') < 0 and 'manage_leds' in self.platform.conf\
and self.platform.conf['manage_leds'] == True:
# Don't need to generate any constraints (?)
# - Just need to map the output of the gpio_simulink2ext to the input of the led_manager
return const
const += [
PortConstraint(self.fullname + '_ext',
self.io_group,
port_index=list(range(self.bitwidth)),
iogroup_index=to_int_list(self.bit_index))
]
#Constrain the I/O (it is assumed that this I/O is not timing critical and set_false_path is used)
#NB: The set_max_delay and set_min_delay is important as Vivado will report that these signals are not
#constrained without it
if self.io_dir == 'in':
const += [
MaxDelayConstraint(sourcepath='[get_ports {%s_ext[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
MinDelayConstraint(sourcepath='[get_ports {%s_ext[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
FalsePathConstraint(sourcepath='[get_ports {%s_ext[*]}]' %
self.fullname)
]
elif self.io_dir == 'out':
const += [
MaxDelayConstraint(destpath='[get_ports {%s_ext[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
MinDelayConstraint(destpath='[get_ports {%s_ext[*]}]' %
self.fullname,
constdelay_ns=1.0)
]
const += [
FalsePathConstraint(destpath='[get_ports {%s_ext[*]}]' %
self.fullname)
]
return const
def gen_constraints(self):
cons = []
# Pin Constraints
cons.append(
PortConstraint('MEZ%s_REFCLK_0_P' % self.mez,
'MEZ%s_REFCLK_0_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_0_N' % self.mez,
'MEZ%s_REFCLK_0_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_1_P' % self.mez,
'MEZ%s_REFCLK_1_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_1_N' % self.mez,
'MEZ%s_REFCLK_1_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_2_P' % self.mez,
'MEZ%s_REFCLK_2_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_2_N' % self.mez,
'MEZ%s_REFCLK_2_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_3_P' % self.mez,
'MEZ%s_REFCLK_3_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_3_N' % self.mez,
'MEZ%s_REFCLK_3_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_PHY11_LANE_RX_P' % self.mez,
'MEZ%s_PHY11_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY11_LANE_RX_N' % self.mez,
'MEZ%s_PHY11_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY12_LANE_RX_P' % self.mez,
'MEZ%s_PHY12_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY12_LANE_RX_N' % self.mez,
'MEZ%s_PHY12_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY21_LANE_RX_P' % self.mez,
'MEZ%s_PHY21_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY21_LANE_RX_N' % self.mez,
'MEZ%s_PHY21_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY22_LANE_RX_P' % self.mez,
'MEZ%s_PHY22_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY22_LANE_RX_N' % self.mez,
'MEZ%s_PHY22_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZZANINE_%s_RESET' % self.mez,
'MEZZANINE_%s_RESET' % self.mez))
cons.append(
PortConstraint('MEZZANINE_%s_CLK_SEL' % self.mez,
'MEZZANINE_%s_CLK_SEL' % self.mez))
cons.append(PortConstraint(
'aux_clk_diff_p',
'aux_clk_diff_p')) #AUX_CLK_P : in std_logic; AU20
cons.append(PortConstraint(
'aux_clk_diff_n',
'aux_clk_diff_n')) #AUX_CLK_N : in std_logic; AV19
cons.append(PortConstraint(
'sync_in_p', 'sync_in_p')) #AUX_SYNCI_P : in std_logic; AT21
cons.append(PortConstraint(
'sync_in_n', 'sync_in_n')) #AUX_SYNCI_N : in std_logic; AU21
cons.append(PortConstraint(
'sync_out_p', 'sync_out_p')) #AUX_SYNCO_P : out std_logic; AW21
cons.append(PortConstraint(
'sync_out_n', 'sync_out_n')) #AUX_SYNCO_N : out std_logic); AY21
# Output Constraints
#set_output_delay -clock [get_clocks FPGA_REFCLK_BUF0_P] -min -add_delay -3.000 [get_ports AUX_SYNCO_P]
#set_output_delay -clock [get_clocks FPGA_REFCLK_BUF0_P] -max -add_delay -3.000 [get_ports AUX_SYNCO_P]
cons.append(
OutputDelayConstraint(
clkname='-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
consttype='min',
constdelay_ns=-3.0,
add_delay_en=True,
portname='sync_out_p'))
cons.append(
OutputDelayConstraint(
clkname='-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
consttype='max',
constdelay_ns=-3.0,
add_delay_en=True,
portname='sync_out_p'))
cons.append(
MultiCycleConstraint(
multicycletype='setup',
sourcepath=
'get_clocks -of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
destpath='get_ports sync_out_p',
multicycledelay=4))
cons.append(
MultiCycleConstraint(
multicycletype='hold',
sourcepath=
'get_clocks -of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
destpath='get_ports sync_out_p',
multicycledelay=3))
#Clock Constraints
#create_clock -period 100.000 -name AUX_CLK_P -waveform {0.000 50.000} [get_ports AUX_CLK_P]
#create_clock -period 100.000 -name AUX_SYNCI_P -waveform {0.000 50.000} [get_ports AUX_SYNCI_P]
#create_clock -period 3.57 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#create_clock -period 3.57 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#create_clock -period 3.57 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#create_clock -period 3.57 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.714 -waveform {0.000 2.857} [get_ports ADC_MEZ_REFCLK_0_P]
#create_clock -period 5.714 -waveform {0.000 2.857} [get_ports ADC_MEZ_REFCLK_1_P]
#create_clock -period 5.714 -waveform {0.000 2.857} [get_ports ADC_MEZ_REFCLK_2_P]
#create_clock -period 5.714 -waveform {0.000 2.857} [get_ports ADC_MEZ_REFCLK_3_P]
cons.append(
ClockConstraint('aux_clk_diff_p',
'aux_clk_diff_p',
period=100.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=50.0))
cons.append(
ClockConstraint('sync_in_p',
'sync_in_p',
period=100.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=50.0))
cons.append(
ClockConstraint(
'%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=3.57,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=1.785))
cons.append(
ClockConstraint(
'%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=3.57,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=1.785))
cons.append(
ClockConstraint(
'%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=3.57,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=1.785))
cons.append(
ClockConstraint(
'%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=3.57,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=1.785))
cons.append(
ClockConstraint('MEZ%s_REFCLK_0_P' % self.mez,
'MEZ%s_REFCLK_0_P' % self.mez,
period=5.714,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.857))
cons.append(
ClockConstraint('MEZ%s_REFCLK_1_P' % self.mez,
'MEZ%s_REFCLK_1_P' % self.mez,
period=5.714,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.857))
cons.append(
ClockConstraint('MEZ%s_REFCLK_2_P' % self.mez,
'MEZ%s_REFCLK_2_P' % self.mez,
period=5.714,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.857))
cons.append(
ClockConstraint('MEZ%s_REFCLK_3_P' % self.mez,
'MEZ%s_REFCLK_3_P' % self.mez,
period=5.714,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.857))
#Clock Group Constraints
#set_clock_groups -asynchronous -group [get_clocks AUX_CLK_P] -group [get_clocks FPGA_REFCLK_BUF0_P]
#set_clock_groups -asynchronous -group [get_clocks AUX_SYNCI_P] -group [get_clocks FPGA_REFCLK_BUF0_P]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'aux_clk_diff_p', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'sync_in_p', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
#False Path Constraints
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -from [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]] -to [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_false_path -from [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]] -to [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_false_path -from [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]] -to [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_false_path -from [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]] -to [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_false_path -from [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK] -to [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]
#set_false_path -from [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK] -to [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]
#set_false_path -from [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK] -to [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]
#set_false_path -from [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK] -to [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]',
destpath=
'[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]',
destpath=
'[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]',
destpath=
'[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]',
destpath=
'[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname,
destpath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]'
))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname,
destpath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]'
))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname,
destpath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]'
))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname,
destpath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]'
))
#Raw Constraints
#create_pblock ADC32RF45_11G2_RX_0
#add_cells_to_pblock [get_pblocks ADC32RF45_11G2_RX_0] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]
#resize_pblock [get_pblocks ADC32RF45_11G2_RX_0] -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}
#create_pblock ADC32RF45_11G2_RX_1
#add_cells_to_pblock [get_pblocks ADC32RF45_11G2_RX_1] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]
#resize_pblock [get_pblocks ADC32RF45_11G2_RX_1] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#create_pblock ADC32RF45_11G2_RX_2
#add_cells_to_pblock [get_pblocks ADC32RF45_11G2_RX_2] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]
#resize_pblock [get_pblocks ADC32RF45_11G2_RX_2] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
#create_pblock ADC32RF45_11G2_RX_3
#add_cells_to_pblock [get_pblocks ADC32RF45_11G2_RX_3] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]
#resize_pblock [get_pblocks ADC32RF45_11G2_RX_3] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_0' %
self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' -add {CLOCKREGION_X1Y7:CLOCKREGION_X1Y7}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_1' %
self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' -add {CLOCKREGION_X0Y5:CLOCKREGION_X0Y5}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' -add {CLOCKREGION_X1Y6:CLOCKREGION_X1Y6}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_2' %
self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y6}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' -add {CLOCKREGION_X1Y5:CLOCKREGION_X1Y5}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_3' %
self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' -add {CLOCKREGION_X0Y7:CLOCKREGION_X0Y7}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' -add {CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}'))
return cons
def gen_constraints(self):
cons = []
# Pin Constraints
cons.append(
PortConstraint('ADC_DATA_IN1',
'ADC_DATA_IN1',
port_index=list(range(self.bits)),
iogroup_index=list(range(self.bits))))
cons.append(
PortConstraint('ADC_DATA_IN2',
'ADC_DATA_IN2',
port_index=list(range(self.bits)),
iogroup_index=list(range(self.bits))))
cons.append(PortConstraint('ADC_CLK_STB_OUT', 'ADC_CLK_STB_OUT'))
#cons.append(PortConstraint('ADC_LA_CLK', 'ADC_LA_CLK'))
#To do: add timing constraints
#Clock Group Constraints
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', 'aux_clk_diff_p', 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', 'sync_in_p', 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
#input constraints
cons.append(
InputDelayConstraint(clkname='ADC_CLK_IN_P',
consttype='min',
constdelay_ns=3.4,
add_delay_en=True,
portname='ADC_DATA_IN1[*]'))
cons.append(
InputDelayConstraint(clkname='ADC_CLK_IN_P',
consttype='max',
constdelay_ns=3.4,
add_delay_en=True,
portname='ADC_DATA_IN1[*]'))
cons.append(
InputDelayConstraint(clkname='ADC_CLK_IN_P',
consttype='min',
constdelay_ns=3.4,
add_delay_en=True,
portname='ADC_DATA_IN2[*]'))
cons.append(
InputDelayConstraint(clkname='ADC_CLK_IN_P',
consttype='max',
constdelay_ns=3.4,
add_delay_en=True,
portname='ADC_DATA_IN2[*]'))
# Output Constraints
#cons.append(OutputDelayConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=-3.0, add_delay_en=True, portname='sync_out_p'))
#cons.append(OutputDelayConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='sync_out_p'))
#False Path Constraints
#cons.append(FalsePathConstraint(destpath='[get_pins {%s/ADC32RF45_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]' % self.fullname))
#cons.append(FalsePathConstraint(destpath='[get_pins {%s/ADC32RF45_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]' % self.fullname))
#cons.append(FalsePathConstraint(destpath='[get_pins {%s/ADC32RF45_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]' % self.fullname))
#cons.append(FalsePathConstraint(destpath='[get_pins {%s/ADC32RF45_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]' % self.fullname))
#cons.append(FalsePathConstraint(destpath='[get_pins {%s/ADC32RF45_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]' % self.fullname))
#cons.append(FalsePathConstraint(destpath='[get_pins {%s/ADC32RF45_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]' % self.fullname))
#cons.append(FalsePathConstraint(destpath='[get_pins {%s/ADC32RF45_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]' % self.fullname))
#cons.append(FalsePathConstraint(destpath='[get_pins {%s/ADC32RF45_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]' % self.fullname))
#Raw Constraints
return cons
def gen_constraints(self):
return [PortConstraint(self.fullname+'_ext', self.io_group, port_index=list(range(self.bitwidth)), iogroup_index=to_int_list(self.bit_index))]
def gen_constraints(self):
cons = []
# -------------------------------------
# PATHS
# -------------------------------------
# RXOUTCLK: ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK
# BUF: ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i
# -------------------------------------
# PIN CONSTRAINTS
# -------------------------------------
cons.append(PortConstraint('MEZ%s_REFCLK_0_P' % self.mez, 'MEZ%s_REFCLK_0_P' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_0_N' % self.mez, 'MEZ%s_REFCLK_0_N' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_1_P' % self.mez, 'MEZ%s_REFCLK_1_P' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_1_N' % self.mez, 'MEZ%s_REFCLK_1_N' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_2_P' % self.mez, 'MEZ%s_REFCLK_2_P' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_2_N' % self.mez, 'MEZ%s_REFCLK_2_N' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_3_P' % self.mez, 'MEZ%s_REFCLK_3_P' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_3_N' % self.mez, 'MEZ%s_REFCLK_3_N' % self.mez))
cons.append(PortConstraint('MEZ%s_PHY11_LANE_RX_P' % self.mez, 'MEZ%s_PHY11_LANE_RX_P' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY11_LANE_RX_N' % self.mez, 'MEZ%s_PHY11_LANE_RX_N' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY12_LANE_RX_P' % self.mez, 'MEZ%s_PHY12_LANE_RX_P' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY12_LANE_RX_N' % self.mez, 'MEZ%s_PHY12_LANE_RX_N' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY21_LANE_RX_P' % self.mez, 'MEZ%s_PHY21_LANE_RX_P' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY21_LANE_RX_N' % self.mez, 'MEZ%s_PHY21_LANE_RX_N' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY22_LANE_RX_P' % self.mez, 'MEZ%s_PHY22_LANE_RX_P' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY22_LANE_RX_N' % self.mez, 'MEZ%s_PHY22_LANE_RX_N' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZZANINE_%s_RESET' % self.mez, 'MEZZANINE_%s_RESET' % self.mez))
cons.append(PortConstraint('MEZZANINE_%s_CLK_SEL' % self.mez, 'MEZZANINE_%s_CLK_SEL' % self.mez))
cons.append(PortConstraint('aux_clk_diff_p','aux_clk_diff_p')) #AUX_CLK_P : in std_logic; AU20
cons.append(PortConstraint('aux_clk_diff_n','aux_clk_diff_n')) #AUX_CLK_N : in std_logic; AV19
cons.append(PortConstraint('sync_in_p','sync_in_p')) #AUX_SYNCI_P : in std_logic; AT21
cons.append(PortConstraint('sync_in_n','sync_in_n')) #AUX_SYNCI_N : in std_logic; AU21
cons.append(PortConstraint('sync_out_p','sync_out_p')) #AUX_SYNCO_P : out std_logic; AW21
cons.append(PortConstraint('sync_out_n','sync_out_n')) #AUX_SYNCO_N : out std_logic); AY21
# -------------------------------------
# INPUT/OUTPUT DELAY CONSTRAINTS
# -------------------------------------
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='sync_in_p'))
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='sync_in_p'))
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='aux_clk_diff_p'))
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='aux_clk_diff_p'))
cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=-3.0, add_delay_en=True, portname='sync_out_p'))
cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='sync_out_p'))
cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=0.1, add_delay_en=True, portname='MEZZANINE_%s_RESET' % self.mez))
cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=0.2, add_delay_en=True, portname='MEZZANINE_%s_RESET' % self.mez))
cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', destpath='get_ports MEZZANINE_%s_RESET' % self.mez, multicycledelay=2))
cons.append(MultiCycleConstraint(multicycletype='hold', sourcepath='get_clocks -of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', destpath='get_ports MEZZANINE_%s_RESET' % self.mez, multicycledelay=1))
# -------------------------------------
# CLOCKS
# -------------------------------------
cons.append(ClockConstraint('%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname,'%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK' % self.fullname, period=3.571, port_en=False, virtual_en=False, waveform_min=0.0, waveform_max=1.785))
cons.append(ClockConstraint('%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname,'%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK' % self.fullname, period=3.571, port_en=False, virtual_en=False, waveform_min=0.0, waveform_max=1.785))
cons.append(ClockConstraint('%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname,'%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK' % self.fullname, period=3.571, port_en=False, virtual_en=False, waveform_min=0.0, waveform_max=1.785))
cons.append(ClockConstraint('%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname,'%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK' % self.fullname, period=3.571, port_en=False, virtual_en=False, waveform_min=0.0, waveform_max=1.785))
cons.append(ClockConstraint('MEZ%s_REFCLK_0_P' % self.mez,'MEZ%s_REFCLK_0_P' % self.mez, period=5.714, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=2.857))
cons.append(ClockConstraint('MEZ%s_REFCLK_1_P' % self.mez,'MEZ%s_REFCLK_1_P' % self.mez, period=5.714, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=2.857))
cons.append(ClockConstraint('MEZ%s_REFCLK_2_P' % self.mez,'MEZ%s_REFCLK_2_P' % self.mez, period=5.714, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=2.857))
cons.append(ClockConstraint('MEZ%s_REFCLK_3_P' % self.mez,'MEZ%s_REFCLK_3_P' % self.mez, period=5.714, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=2.857))
# -------------------------------------
# ASYNCHRONOUS CONSTRAINTS
# -------------------------------------
cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]', destpath='[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname))
cons.append(FalsePathConstraint(sourcepath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]', destpath='[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname))
cons.append(FalsePathConstraint(sourcepath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]', destpath='[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname))
cons.append(FalsePathConstraint(sourcepath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]', destpath='[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT1]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT1]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT1]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT1]]'))
if self.sync_ms == "Master":
cons.append(RawConstraint('set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins %s/adc_pll_i/U0/mmcm_adv_inst/CLKOUT0]]' % self.fullname))
# -------------------------------------
# CDC WAIVER
# -------------------------------------
cons.append(RawConstraint('create_waiver -type CDC -id CDC-11 -from [get_pins skarab_infr/user_fpga_rst_reg/C] -to [get_pins %s/ADC32RF45_11G2_RX_0/tff_adcplllocked/reg_z_reg/D] -user Peralex -description {Confirmed CDC-11 can be ignored in this case}' % self.fullname))
cons.append(RawConstraint('create_waiver -type CDC -id CDC-11 -from [get_pins skarab_infr/user_fpga_rst_reg/C] -to [get_pins %s/ADC32RF45_11G2_RX_1/tff_adcplllocked/reg_z_reg/D] -user Peralex -description {Confirmed CDC-11 can be ignored in this case}' % self.fullname))
cons.append(RawConstraint('create_waiver -type CDC -id CDC-11 -from [get_pins skarab_infr/user_fpga_rst_reg/C] -to [get_pins %s/ADC32RF45_11G2_RX_2/tff_adcplllocked/reg_z_reg/D] -user Peralex -description {Confirmed CDC-11 can be ignored in this case}' % self.fullname))
cons.append(RawConstraint('create_waiver -type CDC -id CDC-11 -from [get_pins skarab_infr/user_fpga_rst_reg/C] -to [get_pins %s/ADC32RF45_11G2_RX_3/tff_adcplllocked/reg_z_reg/D] -user Peralex -description {Confirmed CDC-11 can be ignored in this case}' % self.fullname))
# -------------------------------------
# PBLOCKS
# -------------------------------------
cons.append(RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_0' % self.mez))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' [get_cells -quiet [list '+self.fullname+'/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'))
if self.mez == 0:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}'))
elif self.mez == 1:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}'))
elif self.mez == 2:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}'))
elif self.mez == 3:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' -add {CLOCKREGION_X1Y7:CLOCKREGION_X1Y7}'))
cons.append(RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_1' % self.mez))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' [get_cells -quiet [list '+self.fullname+'/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'))
if self.mez == 0:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' -add {CLOCKREGION_X0Y5:CLOCKREGION_X0Y5}'))
elif self.mez == 1:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}'))
elif self.mez == 2:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}'))
elif self.mez == 3:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' -add {CLOCKREGION_X1Y6:CLOCKREGION_X1Y6}'))
cons.append(RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_2' % self.mez))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' [get_cells -quiet [list '+self.fullname+'/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'))
if self.mez == 0:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y6}'))
elif self.mez == 1:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}'))
elif self.mez == 2:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}'))
elif self.mez == 3:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' -add {CLOCKREGION_X1Y5:CLOCKREGION_X1Y5}'))
cons.append(RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_3' % self.mez))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' [get_cells -quiet [list '+self.fullname+'/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'))
if self.mez == 0:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' -add {CLOCKREGION_X0Y7:CLOCKREGION_X0Y7}'))
elif self.mez == 1:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3}'))
elif self.mez == 2:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}'))
elif self.mez == 3:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' -add {CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}'))
return cons
def gen_constraints(self):
cons = []
cons.append(
PortConstraint(self.fullname + '_adc_clk_p_i ',
'zdok%d_p' % self.zdok_num,
iogroup_index=39))
cons.append(
PortConstraint(self.fullname + '_adc_clk_n_i ',
'zdok%d_n' % self.zdok_num,
iogroup_index=39))
cons.append(
PortConstraint(self.fullname + '_adc_sync_p ',
'zdok%d_p' % self.zdok_num,
iogroup_index=38))
cons.append(
PortConstraint(self.fullname + '_adc_sync_n ',
'zdok%d_n' % self.zdok_num,
iogroup_index=38))
cons.append(
PortConstraint(self.fullname + '_adc_data0_p_i ',
'zdok%d_p' % self.zdok_num,
port_index=list(range(8)),
iogroup_index=list(range(8))))
cons.append(
PortConstraint(self.fullname + '_adc_data0_n_i ',
'zdok%d_n' % self.zdok_num,
port_index=list(range(8)),
iogroup_index=list(range(8))))
cons.append(
PortConstraint(self.fullname + '_adc_data1_p_i ',
'zdok%d_p' % self.zdok_num,
port_index=list(range(8)),
iogroup_index=list(range(10, 18))))
cons.append(
PortConstraint(self.fullname + '_adc_data1_n_i ',
'zdok%d_n' % self.zdok_num,
port_index=list(range(8)),
iogroup_index=list(range(10, 18))))
cons.append(
PortConstraint(self.fullname + '_adc_data2_p_i ',
'zdok%d_p' % self.zdok_num,
port_index=list(range(8)),
iogroup_index=list(range(20, 28))))
cons.append(
PortConstraint(self.fullname + '_adc_data2_n_i ',
'zdok%d_n' % self.zdok_num,
port_index=list(range(8)),
iogroup_index=list(range(20, 28))))
cons.append(
PortConstraint(self.fullname + '_adc_data3_p_i ',
'zdok%d_p' % self.zdok_num,
port_index=list(range(8)),
iogroup_index=list(range(30, 38))))
cons.append(
PortConstraint(self.fullname + '_adc_data3_n_i ',
'zdok%d_n' % self.zdok_num,
port_index=list(range(8)),
iogroup_index=list(range(30, 38))))
cons.append(
PortConstraint(self.fullname + '_adc3wire_clk ',
'zdok%d' % self.zdok_num,
iogroup_index=17))
cons.append(
PortConstraint(self.fullname + '_adc3wire_data ',
'zdok%d' % self.zdok_num,
iogroup_index=18))
cons.append(
PortConstraint(self.fullname + '_adc3wire_data_o ',
'zdok%d' % self.zdok_num,
iogroup_index=19))
cons.append(
PortConstraint(self.fullname + '_adc3wire_spi_rst',
'zdok%d' % self.zdok_num,
iogroup_index=36))
cons.append(
PortConstraint(self.fullname + '_modepin ',
'zdok%d' % self.zdok_num,
iogroup_index=16))
cons.append(
PortConstraint(self.fullname + '_reset ',
'zdok%d' % self.zdok_num,
iogroup_index=37))
# clock constraint with variable period
clkconst = ClockConstraint(self.fullname + '_adc_clk_p_i',
name=self.fullname + '_adc5g_clk',
freq=self.bitclk_rate)
cons.append(clkconst)
cons.append(
RawConstraint(
'set_clock_groups -name async_sysclk_adcclk -asynchronous -group [get_clocks -include_generated_clocks %s_CLK] -group [get_clocks -include_generated_clocks sys_clk0_dcm]'
% clkconst.signal))
return cons
def gen_constraints(self):
cons = []
# leaving the aux constraints here so that we can support them at a later stage.
#cons.append(PortConstraint('AUX_CLK_N','AUX_CLK_N'))
#cons.append(PortConstraint('AUX_CLK_P','AUX_CLK_P'))
#cons.append(PortConstraint('AUX_SYNCO_P','AUX_SYNCO_P'))
#cons.append(PortConstraint('AUX_SYNCI_P','AUX_SYNCI_P'))
#cons.append(PortConstraint('AUX_SYNCO_N','AUX_SYNCO_N'))
#cons.append(PortConstraint('AUX_SYNCI_N', 'AUX_SYNCI_N'))
#Need to extract the period and half period for creating the clock
#Port constraints
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_TX_P',
'MEZ3_' + self.mez3_phy + '_LANE_TX_P',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_TX_N',
'MEZ3_' + self.mez3_phy + '_LANE_TX_N',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_RX_P',
'MEZ3_' + self.mez3_phy + '_LANE_RX_P',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_RX_N',
'MEZ3_' + self.mez3_phy + '_LANE_RX_N',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ3_REFCLK_%s_P' % self.port,
'MEZ3_REFCLK_%s_P' % self.port))
cons.append(
PortConstraint('MEZ3_REFCLK_%s_N' % self.port,
'MEZ3_REFCLK_%s_N' % self.port))
cons.append(
ClockConstraint('MEZ3_REFCLK_%s_P' % self.port,
'MEZ3_REFCLK_%s_P' % self.port,
period=6.4,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=3.2))
cons.append(
RawConstraint('create_pblock MEZ3_' + self.mez3_phy + '_QSFP'))
#cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] [get_cells -quiet [list '+self.fullname+'/IEEE802_3_XL_PHY_0/PHY_inst/RX_CLK_RCC]]'))
#cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] [get_cells -quiet [list '+self.fullname+'/IEEE802_3_XL_PHY_0/PHY_inst/TX_CLK_RCC]]'))
cons.append(
RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_' +
self.mez3_phy + '_QSFP] [get_cells -quiet [list ' +
self.fullname + '/IEEE802_3_XL_PHY_0/PHY_inst]]'))
cons.append(
RawConstraint('resize_pblock [get_pblocks MEZ3_' + self.mez3_phy +
'_QSFP] -add {' + self.clock_region + '}'))
if (self.psize_extend):
cons.append(
RawConstraint('resize_pblock [get_pblocks MEZ3_' +
self.mez3_phy + '_QSFP] -add {' +
self.clock_region2 + '}'))
cons.append(
RawConstraint(
'set_property BEL MMCME2_ADV [get_cells [list ' +
self.fullname +
'/IEEE802_3_XL_lPHY_0/PHY_inst/RX_CLK_RCC/ref_clkB_MMCME2_BASE_inst]]'
))
cons.append(
RawConstraint(
'set_property LOC MMCME2_ADV_X1Y4 [get_cells [list ' +
self.fullname +
'/IEEE802_3_XL_PHY_0/PHY_inst/RX_CLK_RCC/ref_clkB_MMCME2_BASE_inst]]'
))
cons.append(
RawConstraint(
'set_property BEL PLLE2_ADV [get_cells [list ' +
self.fullname +
'/IEEE802_3_XL_PHY_0/PHY_inst/TX_CLK_RCC/PLLE2_BASE_inst]]'
))
cons.append(
RawConstraint(
'set_property LOC PLLE2_ADV_X1Y4 [get_cells [list ' +
self.fullname +
'/IEEE802_3_XL_PHY_0/PHY_inst/TX_CLK_RCC/PLLE2_BASE_inst]]'
))
cons.append(
RawConstraint(
'set_property BEL MMCME2_ADV [get_cells [list skarab_infr/SYS_CLK_MMCM_inst]]'
))
cons.append(
RawConstraint(
'set_property LOC MMCME2_ADV_X1Y3 [get_cells [list skarab_infr/SYS_CLK_MMCM_inst]]'
))
cons.append(
RawConstraint(
'set_property BEL MMCME2_ADV [get_cells [list skarab_infr/USER_CLK_MMCM_inst]]'
))
cons.append(
RawConstraint(
'set_property LOC MMCME2_ADV_X0Y4 [get_cells [list skarab_infr/USER_CLK_MMCM_inst]]'
))
cons.append(
RawConstraint(
'set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets skarab_infr/refclk_0]'
))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins skarab_infr/SYS_CLK_MMCM_inst/CLKOUT0]',
'MEZ3_REFCLK_%s_P' % self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins skarab_infr/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]', 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' %self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(
ClockGroupConstraint('MEZ3_REFCLK_%s_P' % self.port,
'FPGA_EMCCLK2', 'asynchronous'))
cons.append(
ClockGroupConstraint('FPGA_EMCCLK2',
'MEZ3_REFCLK_%s_P' % self.port,
'asynchronous'))
cons.append(
ClockGroupConstraint(
'MEZ3_REFCLK_%s_P' % self.port,
'-of_objects [get_pins skarab_infr/SYS_CLK_MMCM_inst/CLKOUT0]',
'asynchronous'))
cons.append(
ClockGroupConstraint(
'MEZ3_REFCLK_%s_P' % self.port,
'-of_objects [get_pins skarab_infr/USER_CLK_MMCM_inst/CLKOUT0]',
'asynchronous'))
cons.append(
ClockGroupConstraint(
'MEZ3_REFCLK_%s_P' % self.port,
'-of_objects [get_pins skarab_infr/SYS_CLK_MMCM_inst/CLKOUT1]',
'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins skarab_infr/SYS_CLK_MMCM_inst/CLKOUT1]',
'MEZ3_REFCLK_%s_P' % self.port, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins skarab_infr/USER_CLK_MMCM_inst/CLKOUT0]',
'MEZ3_REFCLK_%s_P' % self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('VIRTUAL_clkout0', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('virtual_clock', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'FPGA_EMCCLK2', 'asynchronous'))
#cons.append(ClockGroupConstraint('FPGA_EMCCLK2', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'virtual_clock', 'asynchronous'))
#cons.append(ClockGroupConstraint('VIRTUAL_I', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'VIRTUAL_I','asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(InputDelayConstraint(clkname='MEZ3_REFCLK_%s_P'%self.port, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N'))
#cons.append(InputDelayConstraint(clkname='MEZ3_REFCLK_%s_P'%self.port, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N'))
#cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks MEZ3_REFCLK_%s_P'%self.port, multicycledelay=4))
#cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks MEZ3_REFCLK_%s_P'%self.port, multicycledelay=4))
return cons
def gen_constraints(self):
cons = []
# Pin Constraints
cons.append(
PortConstraint('MEZ%s_REFCLK_0_P' % self.mez,
'MEZ%s_REFCLK_0_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_0_N' % self.mez,
'MEZ%s_REFCLK_0_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_1_P' % self.mez,
'MEZ%s_REFCLK_1_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_1_N' % self.mez,
'MEZ%s_REFCLK_1_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_2_P' % self.mez,
'MEZ%s_REFCLK_2_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_2_N' % self.mez,
'MEZ%s_REFCLK_2_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_3_P' % self.mez,
'MEZ%s_REFCLK_3_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_3_N' % self.mez,
'MEZ%s_REFCLK_3_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_PHY11_LANE_RX_P' % self.mez,
'MEZ%s_PHY11_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY11_LANE_RX_N' % self.mez,
'MEZ%s_PHY11_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY12_LANE_RX_P' % self.mez,
'MEZ%s_PHY12_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY12_LANE_RX_N' % self.mez,
'MEZ%s_PHY12_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY21_LANE_RX_P' % self.mez,
'MEZ%s_PHY21_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY21_LANE_RX_N' % self.mez,
'MEZ%s_PHY21_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY22_LANE_RX_P' % self.mez,
'MEZ%s_PHY22_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY22_LANE_RX_N' % self.mez,
'MEZ%s_PHY22_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZZANINE_%s_RESET' % self.mez,
'MEZZANINE_%s_RESET' % self.mez))
cons.append(
PortConstraint('MEZZANINE_%s_CLK_SEL' % self.mez,
'MEZZANINE_%s_CLK_SEL' % self.mez))
cons.append(PortConstraint(
'aux_clk_diff_p',
'aux_clk_diff_p')) #AUX_CLK_P : in std_logic; AU20
cons.append(PortConstraint(
'aux_clk_diff_n',
'aux_clk_diff_n')) #AUX_CLK_N : in std_logic; AV19
cons.append(PortConstraint(
'sync_in_p', 'sync_in_p')) #AUX_SYNCI_P : in std_logic; AT21
cons.append(PortConstraint(
'sync_in_n', 'sync_in_n')) #AUX_SYNCI_N : in std_logic; AU21
cons.append(PortConstraint(
'sync_out_p', 'sync_out_p')) #AUX_SYNCO_P : out std_logic; AW21
cons.append(PortConstraint(
'sync_out_n', 'sync_out_n')) #AUX_SYNCO_N : out std_logic); AY21
# Output Constraints
#set_output_delay -clock [get_clocks FPGA_REFCLK_BUF0_P] -min -add_delay -3.000 [get_ports AUX_SYNCO_P]
#set_output_delay -clock [get_clocks FPGA_REFCLK_BUF0_P] -max -add_delay -3.000 [get_ports AUX_SYNCO_P]
cons.append(
OutputDelayConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
consttype='min',
constdelay_ns=-3.0,
add_delay_en=True,
portname='sync_out_p'))
cons.append(
OutputDelayConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
consttype='max',
constdelay_ns=-3.0,
add_delay_en=True,
portname='sync_out_p'))
#Clock Constraints
#create_clock -period 100.000 -name AUX_CLK_P -waveform {0.000 50.000} [get_ports AUX_CLK_P]
#create_clock -period 100.000 -name AUX_SYNCI_P -waveform {0.000 50.000} [get_ports AUX_SYNCI_P]
#create_clock -period 5.333 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.333 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.333 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.333 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.333 -waveform {0.000 2.666} [get_ports ADC_MEZ_REFCLK_0_P]
#create_clock -period 5.333 -waveform {0.000 2.666} [get_ports ADC_MEZ_REFCLK_1_P]
#create_clock -period 5.333 -waveform {0.000 2.666} [get_ports ADC_MEZ_REFCLK_2_P]
#create_clock -period 5.333 -waveform {0.000 2.666} [get_ports ADC_MEZ_REFCLK_3_P]
cons.append(
ClockConstraint('aux_clk_diff_p',
'aux_clk_diff_p',
period=100.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=50.0))
cons.append(
ClockConstraint('sync_in_p',
'sync_in_p',
period=100.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=50.0))
cons.append(
ClockConstraint(
'%s/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=5.333,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint(
'%s/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=5.333,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint(
'%s/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=5.333,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint(
'%s/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=5.333,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint('MEZ%s_REFCLK_0_P' % self.mez,
'MEZ%s_REFCLK_0_P' % self.mez,
period=5.333,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint('MEZ%s_REFCLK_1_P' % self.mez,
'MEZ%s_REFCLK_1_P' % self.mez,
period=5.333,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint('MEZ%s_REFCLK_2_P' % self.mez,
'MEZ%s_REFCLK_2_P' % self.mez,
period=5.333,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint('MEZ%s_REFCLK_3_P' % self.mez,
'MEZ%s_REFCLK_3_P' % self.mez,
period=5.333,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
#Clock Group Constraints
#set_clock_groups -asynchronous -group [get_clocks AUX_CLK_P] -group [get_clocks FPGA_REFCLK_BUF0_P]
#set_clock_groups -asynchronous -group [get_clocks AUX_SYNCI_P] -group [get_clocks FPGA_REFCLK_BUF0_P]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'aux_clk_diff_p', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'sync_in_p', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
#False Path Constraints
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]' %
self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]' %
self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]' %
self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]' %
self.fullname))
#Raw Constraints
#create_pblock ADC32RF45_RX_0
#add_cells_to_pblock [get_pblocks ADC32RF45_RX_0] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]
#resize_pblock [get_pblocks ADC32RF45_RX_0] -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}
#create_pblock ADC32RF45_RX_1
#add_cells_to_pblock [get_pblocks ADC32RF45_RX_1] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]
#resize_pblock [get_pblocks ADC32RF45_RX_1] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#create_pblock ADC32RF45_RX_2
#add_cells_to_pblock [get_pblocks ADC32RF45_RX_2] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]
#resize_pblock [get_pblocks ADC32RF45_RX_2] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
#create_pblock ADC32RF45_RX_3
#add_cells_to_pblock [get_pblocks ADC32RF45_RX_3] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]
#resize_pblock [get_pblocks ADC32RF45_RX_3] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_RX_0' % self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' -add {CLOCKREGION_X1Y7:CLOCKREGION_X1Y7}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_RX_1' % self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' -add {CLOCKREGION_X0Y5:CLOCKREGION_X0Y5}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' -add {CLOCKREGION_X1Y6:CLOCKREGION_X1Y6}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_RX_2' % self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y6}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' -add {CLOCKREGION_X1Y5:CLOCKREGION_X1Y5}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_RX_3' % self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' -add {CLOCKREGION_X0Y7:CLOCKREGION_X0Y7}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' -add {CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}'))
return cons
def gen_constraints(self):
cons = []
# ADC SPI interface
cons.append(
PortConstraint('adc0_adc3wire_csn1', 'zdok0', iogroup_index=21))
cons.append(
PortConstraint('adc0_adc3wire_csn2', 'zdok0', iogroup_index=41))
cons.append(
PortConstraint('adc0_adc3wire_csn3', 'zdok0', iogroup_index=3))
cons.append(
PortConstraint('adc0_adc3wire_csn4', 'zdok0', iogroup_index=40))
cons.append(
PortConstraint('adc0_adc3wire_sdata', 'zdok0', iogroup_index=20))
cons.append(
PortConstraint('adc0_adc3wire_sclk', 'zdok0', iogroup_index=2))
# SPI interface for the second zdok, if we're using it...
if self.num_units > 4:
cons.append(
PortConstraint('adc1_adc3wire_csn1', 'zdok1',
iogroup_index=21))
cons.append(
PortConstraint('adc1_adc3wire_csn2', 'zdok1',
iogroup_index=41))
cons.append(
PortConstraint('adc1_adc3wire_csn3', 'zdok1', iogroup_index=3))
cons.append(
PortConstraint('adc1_adc3wire_csn4', 'zdok1',
iogroup_index=40))
cons.append(
PortConstraint('adc1_adc3wire_sdata',
'zdok1',
iogroup_index=20))
cons.append(
PortConstraint('adc1_adc3wire_sclk', 'zdok1', iogroup_index=2))
cons.append(
PortConstraint('adc16_clk_line_p', 'zdok0_p', iogroup_index=39))
cons.append(
PortConstraint('adc16_clk_line_n', 'zdok0_n', iogroup_index=39))
# older zdok revisions need a frame clock...
#ZDOK pins. ZDOK differential index
# 'a' signals
# D7 23
# F5 32
# C5 12
# A5 2
# D11 25
# F9 34
# C9 14
# F7 33
# F15 37
# A15 7
# C13 16
# A13 6
# A19 9
# C19 19
# D17 28
# A17 8
# 'b' signals
# C7 13
# A7 3
# D5 22
# F3 31
# C11 15
# A11 5
# D9 24
# A9 4
# D15 27
# F13 36
# D13 26
# F11 35
# D19 29
# C17 18
# F17 38
# C15 17
a_group = [
23,
32,
12,
2,
25,
34,
14,
33,
37,
7,
16,
6,
9,
19,
28,
8,
]
b_group = [
13,
3,
22,
31,
15,
5,
24,
4,
27,
36,
26,
35,
29,
18,
38,
17,
]
cons.append(
PortConstraint('adc16_ser_a_p',
'zdok0_p',
port_index=list(range(16)),
iogroup_index=a_group))
cons.append(
PortConstraint('adc16_ser_a_n',
'zdok0_n',
port_index=list(range(16)),
iogroup_index=a_group))
cons.append(
PortConstraint('adc16_ser_b_p',
'zdok0_p',
port_index=list(range(16)),
iogroup_index=b_group))
cons.append(
PortConstraint('adc16_ser_b_n',
'zdok0_n',
port_index=list(range(16)),
iogroup_index=b_group))
if self.num_units > 4:
cons.append(
PortConstraint('adc16_ser_a_p',
'zdok1_p',
port_index=list(range(16, 32)),
iogroup_index=a_group))
cons.append(
PortConstraint('adc16_ser_a_n',
'zdok1_n',
port_index=list(range(16, 32)),
iogroup_index=a_group))
cons.append(
PortConstraint('adc16_ser_b_p',
'zdok1_p',
port_index=list(range(16, 32)),
iogroup_index=b_group))
cons.append(
PortConstraint('adc16_ser_b_n',
'zdok1_n',
port_index=list(range(16, 32)),
iogroup_index=b_group))
# clock constraint with variable period
cons.append(
ClockConstraint('adc16_clk_line_p',
name='adc_clk',
freq=self.clock_freq))
return cons
def gen_constraints(self):
cons = []
# shortcuts to handy strings
adcport = 'zdok%d' % self.adc_brd
adcportp = 'zdok%d_p' % self.adc_brd
adcportn = 'zdok%d_n' % self.adc_brd
adcstr = self.fullname + '_'
cons.append(
PortConstraint(adcstr + 'adc_clk_p', adcportp, iogroup_index=39))
cons.append(
PortConstraint(adcstr + 'adc_clk_n', adcportn, iogroup_index=39))
cons.append(
PortConstraint(adcstr + 'adc_sync_p', adcportp, iogroup_index=38))
cons.append(
PortConstraint(adcstr + 'adc_sync_n', adcportn, iogroup_index=38))
cons.append(
PortConstraint(adcstr + 'adc_outofrangei_p',
adcportp,
iogroup_index=18))
cons.append(
PortConstraint(adcstr + 'adc_outofrangei_n',
adcportn,
iogroup_index=18))
cons.append(
PortConstraint(adcstr + 'adc_outofrangeq_p',
adcportp,
iogroup_index=28))
cons.append(
PortConstraint(adcstr + 'adc_outofrangeq_n',
adcportn,
iogroup_index=28))
cons.append(
PortConstraint(adcstr + 'adc_ddrb_p', adcportp, iogroup_index=29))
cons.append(
PortConstraint(adcstr + 'adc_ddrb_n', adcportn, iogroup_index=29))
cons.append(
PortConstraint(adcstr + 'adc_dataeveni_p',
adcportp,
port_index=list(range(8)),
iogroup_index=[11, 13, 15, 17, 31, 33, 35, 37]))
cons.append(
PortConstraint(adcstr + 'adc_dataeveni_n',
adcportn,
port_index=list(range(8)),
iogroup_index=[11, 13, 15, 17, 31, 33, 35, 37]))
cons.append(
PortConstraint(adcstr + 'adc_dataoddi_p',
adcportp,
port_index=list(range(8)),
iogroup_index=[10, 12, 14, 16, 30, 32, 34, 36]))
cons.append(
PortConstraint(adcstr + 'adc_dataoddi_n',
adcportn,
port_index=list(range(8)),
iogroup_index=[10, 12, 14, 16, 30, 32, 34, 36]))
cons.append(
PortConstraint(adcstr + 'adc_dataevenq_p',
adcportp,
port_index=list(range(8)),
iogroup_index=[6, 4, 2, 0, 26, 24, 22, 20]))
cons.append(
PortConstraint(adcstr + 'adc_dataevenq_n',
adcportn,
port_index=list(range(8)),
iogroup_index=[6, 4, 2, 0, 26, 24, 22, 20]))
cons.append(
PortConstraint(adcstr + 'adc_dataoddq_p',
adcportp,
port_index=list(range(8)),
iogroup_index=[7, 5, 3, 1, 27, 25, 23, 21]))
cons.append(
PortConstraint(adcstr + 'adc_dataoddq_n',
adcportn,
port_index=list(range(8)),
iogroup_index=[7, 5, 3, 1, 27, 25, 23, 21]))
cons.append(
PortConstraint(adcstr + 'modepin', adcport, iogroup_index=16))
cons.append(
PortConstraint(adcstr + 'adc3wire_clk', adcport, iogroup_index=17))
cons.append(
PortConstraint(adcstr + 'adc3wire_strobe',
adcport,
iogroup_index=18))
cons.append(
PortConstraint(adcstr + 'adc3wire_data', adcport,
iogroup_index=19))
clkconst = ClockConstraint(adcstr + 'adc_clk_p',
adcstr + '_clk',
freq=self.adc_clk_rate / 4.)
cons.append(clkconst)
cons.append(
RawConstraint(
'set_clock_groups -name async_sysclk_adcclk -asynchronous -group [get_clocks -include_generated_clocks %s] -group [get_clocks -include_generated_clocks sys_clk0_dcm]'
% (clkconst.name)))
cons.append(
RawConstraint(
'set_property DIFF_TERM TRUE [get_ports %sadc_clk_p]' %
adcstr))
cons.append(
RawConstraint(
'set_property DIFF_TERM TRUE [get_ports %sadc_sync_p]' %
adcstr))
cons.append(
RawConstraint(
'set_property DIFF_TERM TRUE [get_ports %sadc_outofrangei_p]' %
adcstr))
cons.append(
RawConstraint(
'set_property DIFF_TERM TRUE [get_ports %sadc_outofrangeq_p]' %
adcstr))
for i in range(8):
cons.append(
RawConstraint(
'set_property DIFF_TERM TRUE [get_ports %sadc_dataeveni_p[%d]]'
% (adcstr, i)))
cons.append(
RawConstraint(
'set_property DIFF_TERM TRUE [get_ports %sadc_dataoddi_p[%d]]'
% (adcstr, i)))
cons.append(
RawConstraint(
'set_property DIFF_TERM TRUE [get_ports %sadc_dataevenq_p[%d]]'
% (adcstr, i)))
cons.append(
RawConstraint(
'set_property DIFF_TERM TRUE [get_ports %sadc_dataoddq_p[%d]]'
% (adcstr, i)))
return cons
def gen_constraints(self):
cons = []
cons.append(
PortConstraint('FLASH1', 'led', port_index=[0], iogroup_index=[6]))
cons.append(
PortConstraint('FLASH2', 'led', port_index=[0], iogroup_index=[7]))
cons.append(
PortConstraint('Q8_CLK1_GTREFCLK_PAD_P_IN',
'Q8_CLK1_GTREFCLK_PAD_P_IN',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('Q8_CLK1_GTREFCLK_PAD_P_IN',
'Q8_CLK1_GTREFCLK_PAD_P_IN',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('RXN_IN',
'RXN_IN',
port_index=list(range(8)),
iogroup_index=list(range(8))))
cons.append(
PortConstraint('RXP_IN',
'RXP_IN',
port_index=list(range(8)),
iogroup_index=list(range(8))))
cons.append(
PortConstraint('TRACK_DATA_OUT',
'TRACK_DATA_OUT',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('TXN_OUT',
'TXN_OUT',
port_index=list(range(8)),
iogroup_index=list(range(8))))
cons.append(
PortConstraint('TXP_OUT',
'TXP_OUT',
port_index=list(range(8)),
iogroup_index=list(range(8))))
cons.append(
PortConstraint('diff_clock_rtl_clk_n',
'diff_clock_rtl_clk_n',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('diff_clock_rtl_clk_p',
'diff_clock_rtl_clk_p',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('gpio_adc_control_tri_o',
'gpio_adc_control_tri_o',
port_index=list(range(6)),
iogroup_index=list(range(6))))
cons.append(
PortConstraint('iic_scl_io',
'iic_scl_io',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('iic_sda_io',
'iic_sda_io',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('reset_rtl',
'reset_rtl',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('uart_rxd',
'uart_rxd',
port_index=[0],
iogroup_index=[0]))
cons.append(
PortConstraint('uart_txd',
'uart_txd',
port_index=[0],
iogroup_index=[0]))
cons.append(
ClockConstraint('Q8_CLK1_GTREFCLK_PAD_P_IN',
name='Q8_CLK1_GTREFCLK_clk',
freq=156.25))
return cons