def INC(cpu: CPU6502):
value = cpu.fetch()
value += 1
cpu.cpu_write(cpu.state.addr_abs, value & 0xff)
cpu.state.set_flag(Flags6502.Z, (value & 0xff) == 0x00)
cpu.state.set_flag(Flags6502.N, value & 0x0080)
return 0
def RRA(cpu: CPU6502):
m = cpu.fetch()
carry = m & 0x01
m = (cpu.state.get_flag(Flags6502.C) << 7) | (m >> 1)
m &= 0xFF
cpu.state.set_flag(Flags6502.C, carry)
_add(cpu, m)
cpu.cpu_write(cpu.state.addr_abs, m & 0xFF)
return 0
def RLA(cpu: CPU6502):
fetched = cpu.fetch() & 0XFF
fetched = (fetched << 1) | cpu.state.get_flag(Flags6502.C)
cpu.state.set_flag(Flags6502.C, fetched & 0xFF00)
cpu.state.a = cpu.state.a & fetched
cpu.state.set_flag(Flags6502.Z, cpu.state.a == 0x00)
cpu.state.set_flag(Flags6502.N, cpu.state.a & 0x80)
cpu.cpu_write(cpu.state.addr_abs, fetched & 0xFF)
return 0
def SRE(cpu: CPU6502):
m = cpu.fetch() & 0xFF
cpu.state.set_flag(Flags6502.C, m & 0x01)
m = (m >> 1) & 0xFF
cpu.state.a ^= m
cpu.state.set_flag(Flags6502.Z, cpu.state.a == 0x00)
cpu.state.set_flag(Flags6502.N, cpu.state.a & 0x80)
cpu.cpu_write(cpu.state.addr_abs, m & 0xFF)
return 0
def SLO(cpu: CPU6502):
m = cpu.fetch() & 0xFF
m <<= 1
cpu.state.a |= (m & 0xff)
cpu.state.set_flag(Flags6502.C, m & 0xFF00)
cpu.state.set_flag(Flags6502.Z, cpu.state.a == 0x00)
cpu.state.set_flag(Flags6502.N, cpu.state.a & 0x80)
cpu.cpu_write(cpu.state.addr_abs, m & 0xFF)
return 0
def LSR(cpu: CPU6502):
fetched = cpu.fetch() & 0xFF
cpu.state.set_flag(Flags6502.C, fetched & 0x01)
fetched = (fetched >> 1) & 0xFF
cpu.state.set_flag(Flags6502.Z, fetched == 0x00)
cpu.state.set_flag(Flags6502.N, 0)
if lookup[cpu.state.opcode].addr_mode == IMP:
cpu.state.a = fetched
else:
cpu.cpu_write(cpu.state.addr_abs, fetched)
return 0
def ROL(cpu: CPU6502):
fetched = cpu.fetch() & 0XFF
fetched = (fetched << 1) | cpu.state.get_flag(Flags6502.C)
cpu.state.set_flag(Flags6502.C, fetched & 0xFF00)
fetched &= 0xFF
cpu.state.set_flag(Flags6502.Z, fetched == 0x00)
cpu.state.set_flag(Flags6502.N, fetched & 0x80)
if lookup[cpu.state.opcode].addr_mode == IMP:
cpu.state.a = fetched
else:
cpu.cpu_write(cpu.state.addr_abs, fetched)
return 0
def ROR(cpu: CPU6502):
fetched = cpu.fetch()
carry = fetched & 0x01
fetched = (cpu.state.get_flag(Flags6502.C) << 7) | (fetched >> 1)
fetched &= 0xFF
cpu.state.set_flag(Flags6502.C, carry)
cpu.state.set_flag(Flags6502.Z, fetched == 0x00)
cpu.state.set_flag(Flags6502.N, fetched & 0x80)
if lookup[cpu.state.opcode].addr_mode == IMP:
cpu.state.a = fetched
else:
cpu.cpu_write(cpu.state.addr_abs, fetched)
return 0
def STY(cpu: CPU6502):
cpu.cpu_write(cpu.state.addr_abs, cpu.state.y)
return 0
def SAX(cpu: CPU6502):
temp = (cpu.state.a & cpu.state.x)
cpu.cpu_write(cpu.state.addr_abs, temp)
return 0