class HDR14(hdr):
family = "J"
inBOM = False
width = cu.inches(0.1)
N = 14
def escape(self):
return
def place(self, dc):
self.chamfered(dc, 6.2, 9.2)
for _ in range(2):
dc.push()
dc.goxy(-1.5 * T, 1.5 * T).left(180)
self.train(dc, self.N // 2, lambda: self.gh(dc), cu.inches(.1))
dc.pop()
dc.right(180)
def escape(self):
ii = cu.inches(.1) / 2
q = math.sqrt((ii ** 2) + (ii ** 2))
for p in self.pads[:4]:
p.w("l 45").forward(q).left(45).forward(1)
for p in self.pads[4:]:
p.w("r 90 f 1")
oo = list(sum(zip(self.pads[4:], self.pads[:4]), ()))
cu.extend2(oo)
return oo
def dazzler_console(dc):
uart_names = ('DTR', 'OUT', 'IN', '3V3', 'CTS', 'GND')
brd.hole(dc.copy().w("r 180 f 4").xy, 2.5, 5.5)
brd.hole(dc.copy().forward(4 + cu.inches(0.5)).xy, 2.5, 5.5)
uart_port = padline(dc, 6)
for p, nm in zip(uart_port.pads, uart_names):
p.setname(nm)
p.copy().goxy(0, 0).text(nm)
uart_port.s("GND").setname("GL2").w("l 90 f 2").wire(layer="GBL")
tt = [uart_port.pads[i].w("i") for i in (2, 1)]
return brd.enriver(tt, -45).wire()
class Feather(dip.dip):
family = "U"
width = cu.inches(.8)
N = 32
N2 = (16, 12)
def place(self, dc):
dip.dip.place(self, dc)
names = "RESET 3V AREF GND A0 A1 A2 A3 A4 A5 SCK MOSI MISO RX TX D4 SDA SCL D5 D6 D9 D10 D11 D12 D13 USB EN BAT"
for p,nm in zip(self.pads, names.split()):
p.setname(nm)
self.s("GND").copy().setname("GL2").thermal(1.3).wire(layer = "GBL")
class Teensy40(dip.dip):
family = "U"
width = cu.inches(.6)
N = 28
def place(self, dc):
dip.dip.place(self, dc)
for i in range(24):
self.pads[i + 1].setname(str(i))
thermal(self.pads[0], "GBL")
thermal(self.pads[-2], "GBL")
thermal(self.pads[-3], "GTL")
class Teensy40(dip.dip):
family = "U"
width = cu.inches(.6)
N = 28
def place(self, dc):
dip.dip.place(self, dc)
for i in range(24):
self.pads[i + 1].setname(str(i))
for n in (0, -2):
p = self.pads[n]
p.setname("GL2").thermal(1.3).wire(layer = "GBL")
self.pads[-1].setname("vin")
def place(self, dc):
self.chamfered(dc, self.width - T, T * (self.N / 2) + 2)
height = T * ((self.N // 2) - 1)
for _ in range(2):
dc.push()
dc.goxy(-self.width / 2, height / 2).left(180)
def gh():
dc.board.hole(dc.xy, .8)
p = dc.copy()
p.part = self.id
p.n_agon(0.8, 60)
p.contact()
self.pads.append(dc.copy())
self.train(dc, self.N // 2, gh, cu.inches(.1))
dc.pop()
dc.right(180)
class W65C02S(dip.dip):
family = "U"
width = cu.inches(.6)
N = 40
def place(self, dc):
dip.dip.place(self, dc)
nms = [
"VPB", "RDY", "PHI1O", "IRQB", "MLB", "NMIB", "SYNC", "VDD", "A0",
"A1", "A2", "A3", "A4", "A5", "A6", "A7", "A8", "A9", "A10", "A11",
"VSS", "A12", "A13", "A14", "A15", "D7", "D6", "D5", "D4", "D3",
"D2", "D1", "D0", "RWB", "NC", "BE", "PHI2", "SOB", "PHI2C", "RESB"
]
assert len(nms) == 40
for p, nm in zip(self.pads, nms):
p.setname(nm)
p.copy().w("r 90 f 3").text(nm)
# p.copy().goxy(0, -3).text(nm)
def escape(self):
self.s("VSS").setlayer("GBL").setname("GL2").thermal(1).wire()
tied = "VDD NMIB IRQB RDY SOB BE".split()
for t in tied:
self.s(t).setname("VCC").thermal(1).wire()
s1 = [
"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "A8", "A9", "A10",
"A11"
]
s2 = [
"A12", "A13", "A14", "A15", "D7", "D6", "D5", "D4", "D3", "D2",
"D1", "D0", "RWB", "PHI2", "RESB"
]
p1 = [self.s(s) for s in s1[::-1]]
[p.left(90).forward(2) for p in p1]
r1 = self.board.enriver90(p1, -90).wire()
p2 = [self.s(s) for s in s2[::-1]]
[p.left(90).forward(2) for p in p2]
r2 = self.board.enriver90(p2, 90).wire()
return r2.join(r1).wire()
def place(self, dc):
self.chamfered(dc, self.width - T, T * (self.N / 2) + 2)
height = T * ((self.N // 2) - 1)
if self.N2 is None:
nps = [self.N // 2, self.N // 2]
else:
nps = self.N2
for np in nps:
dc.push()
dc.goxy(-self.width / 2, height / 2).left(180)
def gh():
dc.board.hole(dc.xy, .8)
p = dc.copy()
p.part = self.id
p.n_agon(0.8, 60)
p.contact()
self.pads.append(dc.copy())
self.train(dc, np, gh, cu.inches(.1))
dc.pop()
dc.right(180)
import math
import cuflow as cu
T = cu.inches(0.1) # tenth on an inch, used throughout
class dip(cu.Part):
N2 = None
def place(self, dc):
self.chamfered(dc, self.width - T, T * (self.N / 2) + 2)
height = T * ((self.N // 2) - 1)
if self.N2 is None:
nps = [self.N // 2, self.N // 2]
else:
nps = self.N2
for np in nps:
dc.push()
dc.goxy(-self.width / 2, height / 2).left(180)
def gh():
dc.board.hole(dc.xy, .8)
p = dc.copy()
p.part = self.id
p.n_agon(0.8, 60)
p.contact()
self.pads.append(dc.copy())
self.train(dc, np, gh, cu.inches(.1))
dc.pop()
dc.right(180)
class PTH(cu.Part):
r = .8
def gh(self, dc):
space=cu.mil(5) * 2.0,
via_hole=0.3,
via=0.6,
via_space=cu.mil(5),
silk=cu.mil(6))
daz = DazzlerSocket(brd.DC((33, 25)).right(90))
daz.labels()
# cu.C0402(brd.DC((70, 20)).right(90), '0.1 uF').escape_2layer()
usb = Amphenol10118194(brd.DC((6, 0)))
mcu = W65C02S(brd.DC((71, 27)))
uart0 = daz.escapesI(["2", "1"], -90).w("r 90").wire()
uart_names = ('DTR', 'OUT', 'IN', '3V3', 'CTS', 'GND')
brd.hole((2, 39 + 4), 2.5, 5.5)
brd.hole((2, 39 - cu.inches(.5) - 4), 2.5, 5.5)
uart_port = padline(brd.DC((2.0, 39.0)).left(180), 6)
for p, nm in zip(uart_port.pads, uart_names):
p.copy().goxy(0, -3).text(nm)
uart_port.pads[5].copy().w("i -")
tt = [uart_port.pads[i].w("i") for i in (2, 1)]
uart1 = brd.enriver(tt, 45).w("f 16 l 45").meet(uart0)
usb.pads[0].left(90).goto(daz.s("5V")).wire(width=0.4)
usb.pads[4].setwidth(0.4).w("i -")
d1 = daz.escapes([str(i) for i in range(3, 15)],
-90).forward(5).right(45).wire()
d2 = daz.escapes([str(i) for i in range(15, 30)],
90).forward(4).left(45).wire()
daz12 = d1.join(d2, 0.5).wire()
37 BCM 26
38 BCM 20 (MOSI)
39 Ground
40 BCM 21 (SCLK)
"""
def thermal(t, layer, d=1.3):
t.setname(layer).thermal(d).wire(layer=layer)
if __name__ == "__main__":
brd = cu.Board((65, 56),
trace=0.2,
space=cu.inches(1 / 20) - 0.2,
via_hole=0.3,
via=0.6,
via_space=cu.mil(5),
silk=cu.mil(6))
WW = 0.6 # wide wire width
dc = brd.DC((3.5 + 29, 56 - 3.5)).left(90)
j1 = dip.HDR40(dc)
for pin in "6 9 14 20 25 30 34 39".split():
thermal(j1.s(pin), "GBL")
for pin in "2 4".split():
thermal(j1.s(pin), "GTL")
# ------------------------------ FTDI conn
ftdi = dip.SIL(brd.DC((3, 65)).right(0), "6")
ftdi_names = ('DTR', 'OUT', 'IN', '3V3', 'CTS', 'GND')
for p, nm in zip(ftdi.pads, ftdi_names):
p.setname(nm)
p.copy().w("l 90 f 2").ltext(nm)
gnd(ftdi.s("GND"))
uart1 = brd.enriver(
[ftdi.pads[t].setlayer('GBL').left(90) for t in (2, 1)],
45).forward(10).wire()
uart0.w("f 1 / f 50").wire()
uart1.meet(uart0)
# ------------------------------ JTAG conn
jtag = dip.SIL(brd.DC((3, 38 - cu.inches(.1))).right(0), "7")
jtag_names = ('TMS', 'TCK', 'TDO', 'TDI', 'PGM', 'GND', 'VCC')
for p, nm in zip(jtag.pads, jtag_names):
p.setname(nm)
p.copy().w("l 90 f 2").ltext(nm)
gnd(jtag.s("GND"))
jtag.s("VCC").thermal(1).wire()
for nm in jtag_names[:5]:
daz.s(nm).forward(2).meet(jtag.s(nm).w("l 45 f 1 l 45 f 4").wire())
# ------------------------------ 5V power
pwr5 = dip.SIL(brd.DC((3, 16 - cu.inches(0.05))).right(0), "2")
for p, nm in zip(pwr5.pads, ("5V", "GND")):
p.setname(nm)
p.copy().w("l 90 f 2").ltext(nm)
gnd(pwr5.s("GND"))
def place(self, dc):
self.chamfered(dc, 18.0, 18)
dc.goxy(-8, cu.inches(0.15)).left(180)
self.train(dc, 4, lambda: self.rpad(dc, 2, 2), cu.inches(0.1))
def escape(self):
pp = self.pads
pp[0].w("i .")
pp[1].setname("GTL").w("i f 1").wire(layer="GTL")
pp[2].w("i f 2").wire().via().setlayer("GBL")
pp[3].w("i f 2").wire().via().setlayer("GBL")
return (pp[2], pp[3])
if __name__ == "__main__":
(xo, yo) = (20, 26)
# (xo, yo) = (4, 4)
brd = cu.Board((50 + xo, 42 + yo),
trace=0.2,
space=cu.inches(1 / 20) - 0.2,
via_hole=0.3,
via=0.6,
via_space=cu.mil(5),
silk=cu.mil(6))
holexy = [(47.2, 2.8), (2.8, 42 - 2.8), (2.8, 2.8), (45, 33.5)]
for x, y in holexy:
brd.hole((x + 2, y + 2), 2.6, 5)
teensy = Teensy40(brd.DC((42, 57)).right(90))
if 0:
daz = DazzlerPogo(brd.DC((25, 21)))
(sda, scl) = EDS(brd.DC((10, 54))).escape()
daz.pads[5].setname("GBL").forward(2).wire(layer="GBL")
