def get_vertical_loop_section_sdfg(section: "VerticalLoopSection") -> SDFG:
from gtc.dace.nodes import HorizontalExecutionLibraryNode
sdfg = SDFG("VerticalLoopSection_" + str(id(section)))
old_state = sdfg.add_state("start_state", is_start_state=True)
for he in section.horizontal_executions:
new_state = sdfg.add_state("HorizontalExecution_" + str(id(he)) + "_state")
sdfg.add_edge(old_state, new_state, InterstateEdge())
new_state.add_node(HorizontalExecutionLibraryNode(oir_node=he))
old_state = new_state
return sdfg
def make_compute_nested_sdfg(parent):
sdfg = SDFG("histogram_compute")
init_state = make_init_buffer_state(sdfg)
compute_state = make_compute_state(sdfg)
finalize_state = make_write_buffer_state(sdfg)
sdfg.add_edge(init_state, compute_state, dace.graph.edges.InterstateEdge())
sdfg.add_edge(compute_state, finalize_state,
dace.graph.edges.InterstateEdge())
return sdfg
def split_condition_interstate_edges(sdfg: dace.SDFG):
edges_to_split = set()
for isedge in sdfg.edges():
if (not isedge.data.is_unconditional()
and len(isedge.data.assignments) > 0):
edges_to_split.add(isedge)
for ise in edges_to_split:
sdfg.remove_edge(ise)
interim = sdfg.add_state()
sdfg.add_edge(ise.src, interim,
dace.InterstateEdge(ise.data.condition))
sdfg.add_edge(interim, ise.dst,
dace.InterstateEdge(assignments=ise.data.assignments))
def make_sdfg(specialize):
if specialize:
sdfg = SDFG("histogram_fpga_parallel_{}_{}x{}".format(
P.get(), H.get(), W.get()))
else:
sdfg = SDFG("histogram_fpga_parallel_{}".format(P.get()))
copy_to_fpga_state = make_copy_to_fpga_state(sdfg)
state = sdfg.add_state("compute")
# Compute module
nested_sdfg = make_compute_nested_sdfg(state)
tasklet = state.add_nested_sdfg(nested_sdfg, sdfg, {"A_pipe_in"},
{"hist_pipe_out"})
A_pipes_out = state.add_stream("A_pipes",
dtype,
shape=(P, ),
transient=True,
storage=StorageType.FPGA_Local)
A_pipes_in = state.add_stream("A_pipes",
dtype,
shape=(P, ),
transient=True,
storage=StorageType.FPGA_Local)
hist_pipes_out = state.add_stream("hist_pipes",
itype,
shape=(P, ),
transient=True,
storage=StorageType.FPGA_Local)
unroll_entry, unroll_exit = state.add_map(
"unroll_compute", {"p": "0:P"},
schedule=dace.ScheduleType.FPGA_Device,
unroll=True)
state.add_memlet_path(unroll_entry, A_pipes_in, memlet=EmptyMemlet())
state.add_memlet_path(hist_pipes_out, unroll_exit, memlet=EmptyMemlet())
state.add_memlet_path(A_pipes_in,
tasklet,
dst_conn="A_pipe_in",
memlet=Memlet.simple(A_pipes_in,
"p",
num_accesses="W*H"))
state.add_memlet_path(tasklet,
hist_pipes_out,
src_conn="hist_pipe_out",
memlet=Memlet.simple(hist_pipes_out,
"p",
num_accesses="num_bins"))
# Read module
a_device = state.add_array("A_device", (H, W),
dtype,
transient=True,
storage=dace.dtypes.StorageType.FPGA_Global)
read_entry, read_exit = state.add_map("read_map", {
"h": "0:H",
"w": "0:W:P"
},
schedule=ScheduleType.FPGA_Device)
a_val = state.add_array("A_val", (P, ),
dtype,
transient=True,
storage=StorageType.FPGA_Local)
read_unroll_entry, read_unroll_exit = state.add_map(
"read_unroll", {"p": "0:P"},
schedule=ScheduleType.FPGA_Device,
unroll=True)
read_tasklet = state.add_tasklet("read", {"A_in"}, {"A_pipe"},
"A_pipe = A_in[p]")
state.add_memlet_path(a_device,
read_entry,
a_val,
memlet=Memlet(a_val,
num_accesses=1,
subset=Indices(["0"]),
vector_length=P.get(),
other_subset=Indices(["h", "w"])))
state.add_memlet_path(a_val,
read_unroll_entry,
read_tasklet,
dst_conn="A_in",
memlet=Memlet.simple(a_val,
"0",
veclen=P.get(),
num_accesses=1))
state.add_memlet_path(read_tasklet,
read_unroll_exit,
read_exit,
A_pipes_out,
src_conn="A_pipe",
memlet=Memlet.simple(A_pipes_out, "p"))
# Write module
hist_pipes_in = state.add_stream("hist_pipes",
itype,
shape=(P, ),
transient=True,
storage=StorageType.FPGA_Local)
hist_device_out = state.add_array(
"hist_device", (num_bins, ),
itype,
transient=True,
storage=dace.dtypes.StorageType.FPGA_Global)
merge_entry, merge_exit = state.add_map("merge", {"nb": "0:num_bins"},
schedule=ScheduleType.FPGA_Device)
merge_reduce = state.add_reduce("lambda a, b: a + b", (0, ),
"0",
schedule=ScheduleType.FPGA_Device)
state.add_memlet_path(hist_pipes_in,
merge_entry,
merge_reduce,
memlet=Memlet.simple(hist_pipes_in,
"0:P",
num_accesses=P))
state.add_memlet_path(merge_reduce,
merge_exit,
hist_device_out,
memlet=dace.memlet.Memlet.simple(
hist_device_out, "nb"))
copy_to_host_state = make_copy_to_host_state(sdfg)
sdfg.add_edge(copy_to_fpga_state, state, dace.graph.edges.InterstateEdge())
sdfg.add_edge(state, copy_to_host_state, dace.graph.edges.InterstateEdge())
return sdfg
