def write_PIA0_A_data(self, cpu_cycles, op_address, address, value):
""" write to 0xff00 -> PIA 0 A side Data reg. """
log.error("%04x| write $%02x (%s) to $%04x -> PIA 0 A side Data reg.\t|%s",
op_address, value, byte2bit_string(value), address,
self.cfg.mem_info.get_shortest(op_address)
)
self.pia_0_A_register.set(value)
def write_PIA0_A_data(self, cpu_cycles, op_address, address, value):
""" write to 0xff00 -> PIA 0 A side Data reg. """
log.error(
"%04x| write $%02x (%s) to $%04x -> PIA 0 A side Data reg.\t|%s",
op_address, value, byte2bit_string(value), address,
self.cfg.mem_info.get_shortest(op_address))
self.pia_0_A_register.set(value)
def write_PIA0_B_data(self, cpu_cycles, op_address, address, value):
""" write to 0xff02 -> PIA 0 B side Data reg. """
log.debug(
# log.info(
"%04x| write $%02x (%s) to $%04x -> PIA 0 B side Data reg.\t|%s",
op_address, value, byte2bit_string(value),
address, self.cfg.mem_info.get_shortest(op_address)
)
self.pia_0_B_data.set(value)
def write_PIA0_B_control(self, cpu_cycles, op_address, address, value):
"""
write to 0xff03 -> PIA 0 B side Control reg.
TODO: Handle IRQ
bit 7 | IRQ 1 (VSYNC) flag
bit 6 | IRQ 2 flag(not used)
bit 5 | Control line 2 (CB2) is an output = 1
bit 4 | Control line 2 (CB2) set by bit 3 = 1
bit 3 | select line MSB of analog multiplexor (MUX): 0 = control line 2 LO / 1 = control line 2 HI
bit 2 | set data direction: 0 = $FF02 is DDR / 1 = $FF02 is normal data lines
bit 1 | control line 1 (CB1): IRQ polarity 0 = IRQ on HI to LO / 1 = IRQ on LO to HI
bit 0 | VSYNC IRQ: 0 = disable IRQ / 1 = enable IRQ
"""
log.critical(
"%04x| write $%02x (%s) to $%04x -> PIA 0 B side Control reg.\t|%s",
op_address, value, byte2bit_string(value),
address, self.cfg.mem_info.get_shortest(op_address)
)
if is_bit_set(value, bit=0):
log.critical(
"%04x| write $%02x (%s) to $%04x -> VSYNC IRQ: enable\t|%s",
op_address, value, byte2bit_string(value),
address, self.cfg.mem_info.get_shortest(op_address)
)
self.cpu.irq_enabled = True
value = set_bit(value, bit=7)
else:
log.critical(
"%04x| write $%02x (%s) to $%04x -> VSYNC IRQ: disable\t|%s",
op_address, value, byte2bit_string(value),
address, self.cfg.mem_info.get_shortest(op_address)
)
self.cpu.irq_enabled = False
if not is_bit_set(value, bit=2):
self.pia_0_B_control.select_pdr()
else:
self.pia_0_B_control.deselect_pdr()
self.pia_0_B_control.set(value)
def read_PIA0_B_control(self, cpu_cycles, op_address, address):
"""
read from 0xff03 -> PIA 0 B side Control reg.
"""
value = self.pia_0_B_control.value
log.error(
"%04x| read $%04x (PIA 0 B side Control reg.) send $%02x (%s) back.\t|%s",
op_address, address, value, byte2bit_string(value),
self.cfg.mem_info.get_shortest(op_address))
return value
def read_PIA0_A_control(self, cpu_cycles, op_address, address):
"""
read from 0xff01 -> PIA 0 A side control register
"""
value = 0xb3
log.error(
"%04x| read $%04x (PIA 0 A side Control reg.) send $%02x (%s) back.\t|%s",
op_address, address, value, byte2bit_string(value),
self.cfg.mem_info.get_shortest(op_address))
return value
def read_PIA0_B_control(self, cpu_cycles, op_address, address):
"""
read from 0xff03 -> PIA 0 B side Control reg.
"""
value = self.pia_0_B_control.value
log.error(
"%04x| read $%04x (PIA 0 B side Control reg.) send $%02x (%s) back.\t|%s",
op_address, address, value, byte2bit_string(value),
self.cfg.mem_info.get_shortest(op_address)
)
return value
def read_PIA0_A_control(self, cpu_cycles, op_address, address):
"""
read from 0xff01 -> PIA 0 A side control register
"""
value = 0xb3
log.error(
"%04x| read $%04x (PIA 0 A side Control reg.) send $%02x (%s) back.\t|%s",
op_address, address, value, byte2bit_string(value),
self.cfg.mem_info.get_shortest(op_address)
)
return value
def write_PIA0_B_data(self, cpu_cycles, op_address, address, value):
""" write to 0xff02 -> PIA 0 B side Data reg. """
log.debug(
# log.info(
"%04x| write $%02x (%s) to $%04x -> PIA 0 B side Data reg.\t|%s",
op_address,
value,
byte2bit_string(value),
address,
self.cfg.mem_info.get_shortest(op_address))
self.pia_0_B_data.set(value)
def write_PIA0_B_control(self, cpu_cycles, op_address, address, value):
"""
write to 0xff03 -> PIA 0 B side Control reg.
TODO: Handle IRQ
bit 7 | IRQ 1 (VSYNC) flag
bit 6 | IRQ 2 flag(not used)
bit 5 | Control line 2 (CB2) is an output = 1
bit 4 | Control line 2 (CB2) set by bit 3 = 1
bit 3 | select line MSB of analog multiplexor (MUX): 0 = control line 2 LO / 1 = control line 2 HI
bit 2 | set data direction: 0 = $FF02 is DDR / 1 = $FF02 is normal data lines
bit 1 | control line 1 (CB1): IRQ polarity 0 = IRQ on HI to LO / 1 = IRQ on LO to HI
bit 0 | VSYNC IRQ: 0 = disable IRQ / 1 = enable IRQ
"""
log.critical(
"%04x| write $%02x (%s) to $%04x -> PIA 0 B side Control reg.\t|%s",
op_address, value, byte2bit_string(value), address,
self.cfg.mem_info.get_shortest(op_address))
if is_bit_set(value, bit=0):
log.critical(
"%04x| write $%02x (%s) to $%04x -> VSYNC IRQ: enable\t|%s",
op_address, value, byte2bit_string(value), address,
self.cfg.mem_info.get_shortest(op_address))
self.cpu.irq_enabled = True
value = set_bit(value, bit=7)
else:
log.critical(
"%04x| write $%02x (%s) to $%04x -> VSYNC IRQ: disable\t|%s",
op_address, value, byte2bit_string(value), address,
self.cfg.mem_info.get_shortest(op_address))
self.cpu.irq_enabled = False
if not is_bit_set(value, bit=2):
self.pia_0_B_control.select_pdr()
else:
self.pia_0_B_control.deselect_pdr()
self.pia_0_B_control.set(value)
def read_PIA0_B_data(self, cpu_cycles, op_address, address):
"""
read from 0xff02 -> PIA 0 B side Data reg.
bit 7 | PB7 | keyboard matrix column 8
bit 6 | PB6 | keyboard matrix column 7 / ram size output
bit 5 | PB5 | keyboard matrix column 6
bit 4 | PB4 | keyboard matrix column 5
bit 3 | PB3 | keyboard matrix column 4
bit 2 | PB2 | keyboard matrix column 3
bit 1 | PB1 | keyboard matrix column 2
bit 0 | PB0 | keyboard matrix column 1
bits 0-7 also printer data lines
"""
value = self.pia_0_B_data.value # $ff02
log.debug(
"%04x| read $%04x (PIA 0 B side Data reg.) send $%02x (%s) back.\t|%s",
op_address, address, value, byte2bit_string(value),
self.cfg.mem_info.get_shortest(op_address))
return value
def read_PIA0_B_data(self, cpu_cycles, op_address, address):
"""
read from 0xff02 -> PIA 0 B side Data reg.
bit 7 | PB7 | keyboard matrix column 8
bit 6 | PB6 | keyboard matrix column 7 / ram size output
bit 5 | PB5 | keyboard matrix column 6
bit 4 | PB4 | keyboard matrix column 5
bit 3 | PB3 | keyboard matrix column 4
bit 2 | PB2 | keyboard matrix column 3
bit 1 | PB1 | keyboard matrix column 2
bit 0 | PB0 | keyboard matrix column 1
bits 0-7 also printer data lines
"""
value = self.pia_0_B_data.value # $ff02
log.debug(
"%04x| read $%04x (PIA 0 B side Data reg.) send $%02x (%s) back.\t|%s",
op_address, address, value, byte2bit_string(value),
self.cfg.mem_info.get_shortest(op_address)
)
return value
def write_PIA0_A_control(self, cpu_cycles, op_address, address, value):
"""
write to 0xff01 -> PIA 0 A side control register
TODO: Handle IRQ
bit 7 | IRQ 1 (HSYNC) flag
bit 6 | IRQ 2 flag(not used)
bit 5 | Control line 2 (CA2) is an output = 1
bit 4 | Control line 2 (CA2) set by bit 3 = 1
bit 3 | select line LSB of analog multiplexor (MUX): 0 = control line 2 LO / 1 = control line 2 HI
bit 2 | set data direction: 0 = $FF00 is DDR / 1 = $FF00 is normal data lines
bit 1 | control line 1 (CA1): IRQ polarity 0 = IRQ on HI to LO / 1 = IRQ on LO to HI
bit 0 | HSYNC IRQ: 0 = disabled IRQ / 1 = enabled IRQ
"""
log.error(
"%04x| write $%02x (%s) to $%04x -> PIA 0 A side Control reg.\t|%s",
op_address, value, byte2bit_string(value), address,
self.cfg.mem_info.get_shortest(op_address))
if not is_bit_set(value, bit=2):
self.pia_0_A_register.select_pdr()
else:
self.pia_0_A_register.deselect_pdr()
def write_PIA0_A_control(self, cpu_cycles, op_address, address, value):
"""
write to 0xff01 -> PIA 0 A side control register
TODO: Handle IRQ
bit 7 | IRQ 1 (HSYNC) flag
bit 6 | IRQ 2 flag(not used)
bit 5 | Control line 2 (CA2) is an output = 1
bit 4 | Control line 2 (CA2) set by bit 3 = 1
bit 3 | select line LSB of analog multiplexor (MUX): 0 = control line 2 LO / 1 = control line 2 HI
bit 2 | set data direction: 0 = $FF00 is DDR / 1 = $FF00 is normal data lines
bit 1 | control line 1 (CA1): IRQ polarity 0 = IRQ on HI to LO / 1 = IRQ on LO to HI
bit 0 | HSYNC IRQ: 0 = disabled IRQ / 1 = enabled IRQ
"""
log.error(
"%04x| write $%02x (%s) to $%04x -> PIA 0 A side Control reg.\t|%s",
op_address, value, byte2bit_string(value), address,
self.cfg.mem_info.get_shortest(op_address)
)
if not is_bit_set(value, bit=2):
self.pia_0_A_register.select_pdr()
else:
self.pia_0_A_register.deselect_pdr()
