# board has MISO=PB3, MOSI=PB2, SS=PB0, SCK=PB1, CRESET=PB6 & POWER=C2.
#
import fl
VID_PID = "1D50:602B:0001"
PROG_CONFIG = "B3B2B0B1"
handle = fl.FLHandle()
try:
fl.flInitialise(0)
# Connect, reset the board, open SPI interface & get SS port:
handle = fl.flOpen(VID_PID)
fl.flMultiBitPortAccess(handle, "B6-,C2-") # RESET low & cut the power
fl.flSleep(10)
fl.flSingleBitPortAccess(handle, 2, 2, fl.PIN_HIGH) # power on in RESET
fl.progOpen(handle, PROG_CONFIG)
(port, bit) = fl.progGetPort(handle, fl.LP_SS)
fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_HIGH)
# Send JEDEC device-id command, retrieve three bytes back
fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_LOW)
fl.spiSend(handle, b"\x9F", fl.SPI_MSBFIRST)
bs = fl.spiRecv(handle, 3, fl.SPI_MSBFIRST)
print("JEDEC ID: {}".format(
" ".join(["{:02X}".format(b) for b in bs])))
fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_HIGH)
# Close SPI interface, release reset and close connection
fl.progClose(handle)
fl.flMultiBitPortAccess(handle, "B6?") # release RESET
print("Awaiting...")
fl.flAwaitDevice(VID_PID, 600)
conn = fl.flOpen(VID_PID)
fl.flSingleBitPortAccess(conn, 3, 7, fl.PIN_LOW)
print("flMultiBitPortAccess() returned {:032b}".format(
fl.flMultiBitPortAccess(conn, "D7+")))
fl.flSleep(100)
print("flGetFirmwareID(): {:04X}".format(fl.flGetFirmwareID(conn)))
print("flGetFirmwareVersion(): {:08X}".format(fl.flGetFirmwareVersion(conn)))
print("flIsNeroCapable(): {}".format(fl.flIsNeroCapable(conn)))
print("flIsCommCapable(): {}".format(fl.flIsCommCapable(conn, CONDUIT)))
fl.progOpen(conn, PROG_CONFIG)
print("progGetPort(): {")
(port, bit) = fl.progGetPort(conn, fl.LP_MISO)
print(" MISO: {:c}{}".format(ord('A')+port, bit))
(port, bit) = fl.progGetPort(conn, fl.LP_MOSI)
print(" MOSI: {:c}{}".format(ord('A')+port, bit))
(port, bit) = fl.progGetPort(conn, fl.LP_SS)
print(" SS: {:c}{}".format(ord('A')+port, bit))
(port, bit) = fl.progGetPort(conn, fl.LP_SCK)
print(" SCK: {:c}{}".format(ord('A')+port, bit))
print("}")
fl.jtagClockFSM(conn, 0x0000005F, 9)
fl.jtagShiftInOnly(conn, 32, BYTE_ARRAY)
bs = fl.jtagShiftInOut(conn, 128, fl.SHIFT_ONES)
print("jtagShiftInOut() got {} bytes: {{\n {}\n}}".format(
import argparse
print("FPGALink Python JTAG Example Copyright (C) 2014 Chris McClelland\n")
parser = argparse.ArgumentParser(description='Load FX2LP firmware, load the FPGA, interact with the FPGA.')
parser.add_argument('-v', action="store", nargs=1, required=True, metavar="<VID:PID>", help="VID, PID and opt. dev ID (e.g 1D50:602B:0001)")
parser.add_argument('-q', action="store", nargs=1, required=True, metavar="<jtagPorts>", help="query the JTAG chain")
argList = parser.parse_args()
vp = argList.v[0]
jtagPorts = argList.q[0]
handle = fl.FLHandle()
try:
fl.flInitialise(0)
handle = fl.flOpen(vp)
fl.progOpen(handle, jtagPorts)
# Try special-purpose enum:
fl.jtagClockFSM(handle, 0x0000005F, 9)
bs = fl.jtagShiftInOut(handle, 64, fl.SHIFT_ZEROS)
print("TDO data, given 64 zeros:\n {}".format(
" ".join(["{:02X}".format(b) for b in bs])))
# Try explicit bytes:
fl.jtagClockFSM(handle, 0x0000005F, 9)
bs = fl.jtagShiftInOut(handle, 128, b"\xFF\xFF\xFF\xFF\x00\x00\x00\x00\xCA\xFE\xBA\xBE\xDE\xAD\xBE\xEF")
print("TDO data, given 128 explicit bits:\n {}".format(
" ".join(["{:02X}".format(b) for b in bs])))
fl.progClose(handle)
# board has MISO=PB3, MOSI=PB2, SS=PB0, SCK=PB1, CRESET=PB6 & POWER=C2.
#
import fl
VID_PID = "1D50:602B:0001"
PROG_CONFIG = "B3B2B0B1"
handle = fl.FLHandle()
try:
fl.flInitialise(0)
# Connect, reset the board, open SPI interface & get SS port:
handle = fl.flOpen(VID_PID)
fl.flMultiBitPortAccess(handle, "B6-,C2-") # RESET low & cut the power
fl.flSleep(10)
fl.flSingleBitPortAccess(handle, 2, 2, fl.PIN_HIGH) # power on in RESET
fl.progOpen(handle, PROG_CONFIG)
(port, bit) = fl.progGetPort(handle, fl.LP_SS)
fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_HIGH)
# Send JEDEC device-id command, retrieve three bytes back
fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_LOW)
fl.spiSend(handle, b"\x9F", fl.SPI_MSBFIRST)
bs = fl.spiRecv(handle, 3, fl.SPI_MSBFIRST)
print("JEDEC ID: {}".format(" ".join(["{:02X}".format(b) for b in bs])))
fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_HIGH)
# Close SPI interface, release reset and close connection
fl.progClose(handle)
fl.flMultiBitPortAccess(handle, "B6?") # release RESET
except fl.FLException as ex:
parser.add_argument('-q',
action="store",
nargs=1,
required=True,
metavar="<jtagPorts>",
help="query the JTAG chain")
argList = parser.parse_args()
vp = argList.v[0]
jtagPorts = argList.q[0]
handle = fl.FLHandle()
try:
fl.flInitialise(0)
handle = fl.flOpen(vp)
fl.progOpen(handle, jtagPorts)
# Try special-purpose enum:
fl.jtagClockFSM(handle, 0x0000005F, 9)
bs = fl.jtagShiftInOut(handle, 64, fl.SHIFT_ZEROS)
print("TDO data, given 64 zeros:\n {}".format(" ".join(
["{:02X}".format(b) for b in bs])))
# Try explicit bytes:
fl.jtagClockFSM(handle, 0x0000005F, 9)
bs = fl.jtagShiftInOut(
handle, 128,
b"\xFF\xFF\xFF\xFF\x00\x00\x00\x00\xCA\xFE\xBA\xBE\xDE\xAD\xBE\xEF")
print("TDO data, given 128 explicit bits:\n {}".format(" ".join(
["{:02X}".format(b) for b in bs])))