def convert_multiplier():
BITS = 35
a, b = create_signals(2, BITS, signed=True, delay=None)
p = create_signals(1, 2 * BITS, signed=True, delay=None)
clk, rst = create_clock_reset()
toVHDL(mult.Multiplier35Bit, a, b, p, clk, rst)
def convert_tx():
cs1, valid1, user1, cs2, valid2, user2, frame0, ce_word, ce_bit, \
ce_bp, sdata, clk, rst = create_signals(13)
audio_ch1, audio_ch2 = create_signals(2, 24, signed=True)
toVHDL(AES3_TX, audio_ch1, cs1, valid1, user1, audio_ch2, cs2, valid2,
user2, frame0, ce_word, ce_bit, ce_bp, sdata, clk, rst)
def convert_multiplier():
BITS = 35
a, b = create_signals(2, BITS, signed=True, delay=None)
p = create_signals(1, 2 * BITS, signed=True, delay=None)
clk, rst = create_clock_reset()
toVHDL(mult.Multiplier35Bit, a, b, p, clk, rst)
def convert_receiver():
left, right = create_signals(2, 32, signed=True, delay=None)
# left, right = [Signal(intbv(0)[32:]) for _ in range(2)]
left_ready, right_ready, sdata, ws, sclk, reset = create_signals(6, delay=None)
toVHDL(I2S_Receiver, sdata, ws, left, right, left_ready, right_ready, sclk,
reset)
def convert_transmitter():
left, right = create_signals(2, 32, signed=True, delay=None)
# left, right = [Signal(intbv(0)[32:]) for _ in range(2)]
load_left, load_right, sdata, ws, sclk, reset = create_signals(6, delay=None)
toVHDL(I2S_Transmitter, left, right, load_left, load_right, sdata, ws, sclk,
reset)
def convert_receiver():
left, right = create_signals(2, 32, signed=True, delay=None)
# left, right = [Signal(intbv(0)[32:]) for _ in range(2)]
left_ready, right_ready, sdata, ws, sclk, reset = create_signals(
6, delay=None)
toVHDL(I2S_Receiver, sdata, ws, left, right, left_ready, right_ready, sclk,
reset)
def convert_transmitter():
left, right = create_signals(2, 32, signed=True, delay=None)
# left, right = [Signal(intbv(0)[32:]) for _ in range(2)]
load_left, load_right, sdata, ws, sclk, reset = create_signals(6,
delay=None)
toVHDL(I2S_Transmitter, left, right, load_left, load_right, sdata, ws,
sclk, reset)
def convert_rx():
din, valid1, user1, cs1, out_en, valid2, user2, cs2, parity_error, frame0, \
locked, clk, rst = create_signals(13)
audio_ch1, audio_ch2 = create_signals(2, 24, signed=True)
frames = create_signals(1, 8)
toVHDL(AES3_RX_DEMUXED, din, audio_ch1, valid1, user1, cs1, out_en,
audio_ch2, valid2, user2, cs2, parity_error, frames, frame0, locked,
clk, rst)
def convert_addressable_multiplier():
BITS = 35
ADDRESSES = 3
a, b = create_signals(2, BITS, signed=True, delay=None)
p = create_signals(1, 2 * BITS, signed=True, delay=None)
address_in, address_out = create_signals(2, (0, ADDRESSES + 1), mod=True)
ce = create_signals(1)
clk, rst = create_clock_reset()
toVHDL(mult.AddressableMultiplier35Bit, a, b, p, address_in, address_out, ce, clk, rst)
def convert_three_port_multiplier():
BITS = 35
a, b, c, d, e, f = create_signals(6, BITS, signed=True, delay=None)
load = create_signals(1, (0, 4))
clk_ena = create_signals(1)
clk, rst = create_clock_reset()
ab_rdy, cd_rdy, ef_rdy = create_signals(3)
ab, cd, ef = create_signals(3, 2 * BITS, signed=True, delay=None)
toVHDL(mult.ThreePortMultiplier35Bit, a, b, c, d, e, f, load, clk_ena, clk, rst, ab, ab_rdy, cd, cd_rdy, ef, ef_rdy)
def convert_three_port_multiplier():
BITS = 35
a, b, c, d, e, f = create_signals(6, BITS, signed=True, delay=None)
load = create_signals(1, (0, 4))
clk_ena = create_signals(1)
clk, rst = create_clock_reset()
ab_rdy, cd_rdy, ef_rdy = create_signals(3)
ab, cd, ef = create_signals(3, 2 * BITS, signed=True, delay=None)
toVHDL(mult.ThreePortMultiplier35Bit, a, b, c, d, e, f, load, clk_ena, clk,
rst, ab, ab_rdy, cd, cd_rdy, ef, ef_rdy)
def convert_addressable_multiplier():
BITS = 35
ADDRESSES = 3
a, b = create_signals(2, BITS, signed=True, delay=None)
p = create_signals(1, 2 * BITS, signed=True, delay=None)
address_in, address_out = create_signals(2, (0, ADDRESSES + 1), mod=True)
ce = create_signals(1)
clk, rst = create_clock_reset()
toVHDL(mult.AddressableMultiplier35Bit, a, b, p, address_in, address_out,
ce, clk, rst)
def convert_shared_multiplier():
# @TODO (michiel): This fails
inputs = create_signals(6, 35, signed=True, delay=None)
load = create_signals(1, 2, delay=None)
p_sigs = create_signals(3, 2 * 35, signed=True, delay=None)
p_rdys = create_signals(3, delay=None)
ce = create_signals(1)
clk, rst = create_clock_reset()
left, right = create_signals(2, 32, signed=True, delay=None)
toVHDL(mult.SharedMultiplier, inputs[:3], inputs[3:], load, ce, clk, rst, p_sigs, p_rdys)
def convert_shared_multiplier():
# @TODO (michiel): This fails
inputs = create_signals(6, 35, signed=True, delay=None)
load = create_signals(1, 2, delay=None)
p_sigs = create_signals(3, 2 * 35, signed=True, delay=None)
p_rdys = create_signals(3, delay=None)
ce = create_signals(1)
clk, rst = create_clock_reset()
left, right = create_signals(2, 32, signed=True, delay=None)
toVHDL(mult.SharedMultiplier, inputs[:3], inputs[3:], load, ce, clk, rst,
p_sigs, p_rdys)
def convert():
data = Signal(intbv(0)[3:])
h_sync, v_sync, clk, rst = [Signal(False) for _ in range(4)]
r, g, b = [Signal(intbv(0)[8:]) for _ in range(3)]
toVHDL(VGA_Controller, data, h_sync, v_sync, r, g, b, clk, rst)
def convert():
data = Signal(intbv(0)[3:])
h_sync, v_sync, clk, rst = [Signal(False) for _ in range(4)]
r, g, b = [Signal(intbv(0)[8:]) for _ in range(3)]
toVHDL(VGA_Controller, data, h_sync, v_sync, r, g, b, clk, rst)
def convert_p2s_msb():
i, o = create_signals(2, 8, signed=True)
load = create_signals(1)
clk, rst = create_clock_reset()
toVHDL(p2s.p2s_msb, i, load, o, clk, rst)
def convert_p2s_msb():
i, o = create_signals(2, 8, signed=True)
load = create_signals(1)
clk, rst = create_clock_reset()
toVHDL(p2s.p2s_msb, i, load, o, clk, rst)
def convert():
we, clk = [Signal(False) for _ in range(2)]
# addr = Signal(intbv(0, min=0, max=256))
din, dout = [Signal(intbv(0, min=-64, max=64)) for _ in range(2)]
toVHDL(ShiftRegister, din, we, dout, clk)
