def __init__(self):
# sdram
sdram_module = MT48LC4M16(75 * 1000000)
sdram_phy_settings = sdram.PhySettings(memtype="SDR",
dfi_databits=1 * 16,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0)
self.submodules.sdram_phy = SDRAMPHYSim(sdram_module,
sdram_phy_settings)
self.submodules.sdram_core = SDRAMCore(
self.sdram_phy, sdram_module.geom_settings,
sdram_module.timing_settings, LASMIconSettings(with_refresh=False))
# dma writer
self.submodules.dma_writer = dma_lasmi.Writer(
self.sdram_core.crossbar.get_master())
# dma reader
self.submodules.dma_reader = EncoderDMAReader(
self.sdram_core.crossbar.get_master())
self.comb += self.dma_reader.source.ack.eq(1)
def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)
lasmim = self.sdram.crossbar.get_master()
self.submodules.encoder_reader = EncoderDMAReader(lasmim)
self.submodules.encoder_cdc = RenameClockDomains(
AsyncFIFO([("data", 128)], 4), {
"write": "sys",
"read": "encoder"
})
self.submodules.encoder_buffer = RenameClockDomains(
EncoderBuffer(), "encoder")
self.submodules.encoder_fifo = RenameClockDomains(
SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16),
"encoder")
self.submodules.encoder = Encoder(platform)
encoder_port = self.ethcore.udp.crossbar.get_port(8000, 8)
self.submodules.encoder_streamer = UDPStreamer(
convert_ip("192.168.1.15"), 8000)
self.comb += [
platform.request("user_led", 0).eq(self.encoder_reader.source.stb),
platform.request("user_led", 1).eq(self.encoder_reader.source.ack),
Record.connect(self.encoder_reader.source, self.encoder_cdc.sink),
Record.connect(self.encoder_cdc.source, self.encoder_buffer.sink),
Record.connect(self.encoder_buffer.source, self.encoder_fifo.sink),
Record.connect(self.encoder_fifo.source, self.encoder.sink),
Record.connect(self.encoder.source, self.encoder_streamer.sink),
Record.connect(self.encoder_streamer.source, encoder_port.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]),
self.encoder.bus)
self.add_memory_region("encoder",
self.mem_map["encoder"] + self.shadow_base,
0x2000)
def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)
lasmim = self.sdram.crossbar.get_master()
self.submodules.encoder_reader = EncoderDMAReader(lasmim)
self.submodules.encoder_cdc = RenameClockDomains(AsyncFIFO([("data", 128)], 4),
{"write": "sys", "read": "encoder"})
self.submodules.encoder_buffer = RenameClockDomains(EncoderBuffer(), "encoder")
self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16), "encoder")
self.submodules.encoder = Encoder(platform)
self.submodules.usb_streamer = USBStreamer(platform, platform.request("fx2"))
self.comb += [
Record.connect(self.encoder_reader.source, self.encoder_cdc.sink),
Record.connect(self.encoder_cdc.source, self.encoder_buffer.sink),
Record.connect(self.encoder_buffer.source, self.encoder_fifo.sink),
Record.connect(self.encoder_fifo.source, self.encoder.sink),
Record.connect(self.encoder.source, self.usb_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), self.encoder.bus)
self.add_memory_region("encoder", self.mem_map["encoder"]+self.shadow_base, 0x2000)
platform.add_platform_command("""
NET "{usb_clk}" TNM_NET = "GRPusb_clk";
TIMESPEC "TSise_sucks11" = FROM "GRPusb_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks12" = FROM "GRPsys_clk" TO "GRPusb_clk" TIG;
""", usb_clk=platform.lookup_request("fx2").ifclk)