def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_bank_ctrl")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.reset = self.reset("reset")
self.packet_wr_en = self.input("packet_wr_en", 1)
self.packet_wr_addr = self.input("packet_wr_addr",
self._params.bank_addr_width)
self.packet_wr_data = self.input("packet_wr_data",
self._params.bank_data_width)
self.packet_wr_data_bit_sel = self.input("packet_wr_data_bit_sel",
self._params.bank_data_width)
self.packet_rd_en = self.input("packet_rd_en", 1)
self.packet_rd_addr = self.input("packet_rd_addr",
self._params.bank_addr_width)
self.packet_rd_data = self.output("packet_rd_data",
self._params.bank_data_width)
self.packet_rd_data_valid = self.output("packet_rd_data_valid", 1)
self.mem_rd_en = self.output("mem_rd_en", 1)
self.mem_wr_en = self.output("mem_wr_en", 1)
self.mem_addr = self.output("mem_addr", self._params.bank_addr_width)
self.mem_data_in = self.output("mem_data_in",
self._params.bank_data_width)
self.mem_data_in_bit_sel = self.output("mem_data_in_bit_sel",
self._params.bank_data_width)
self.mem_data_out = self.input("mem_data_out",
self._params.bank_data_width)
self.bank_cfg_ifc = GlbConfigInterface(
addr_width=self._params.bank_addr_width,
data_width=self._params.axi_data_width)
self.if_sram_cfg_s = self.interface(self.bank_cfg_ifc.slave,
f"if_sram_cfg_s",
is_port=True)
self.bank_ctrl_pipeline_depth = self._params.glb_bank_memory_pipeline_depth + \
self._params.sram_gen_pipeline_depth + self._params.sram_gen_output_pipeline_depth + 1
# local variables
self.sram_cfg_rd_data_r = self.var("sram_cfg_rd_data_r",
self._params.axi_data_width)
self.sram_cfg_rd_addr_sel_d = self.var("sram_cfg_rd_addr_sel_d", 1)
self.packet_rd_data_r = self.var("packet_rd_data_r",
self._params.bank_data_width)
self.add_rd_en_pipeline()
self.add_always(self.mem_signal_logic)
self.add_always(self.packet_rd_data_ff)
self.add_always(self.packet_rd_data_logic)
self.add_sram_cfg_rd_addr_sel_pipeline()
self.add_always(self.sram_cfg_rd_data_ff)
self.add_always(self.sram_cfg_rd_data_logic)
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_core_proc_router")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.reset = self.reset("reset")
self.glb_tile_id = self.input("glb_tile_id",
self._params.tile_sel_addr_width)
self.packet_w2e_wsti = self.input("packet_w2e_wsti",
self.header.packet_t)
self.packet_e2w_wsto = self.output("packet_e2w_wsto",
self.header.packet_t)
self.packet_e2w_esti = self.input("packet_e2w_esti",
self.header.packet_t)
self.packet_w2e_esto = self.output("packet_w2e_esto",
self.header.packet_t)
self.wr_packet_pr2sw = self.output("wr_packet_pr2sw",
self.header.wr_packet_t)
self.rdrq_packet_pr2sw = self.output("rdrq_packet_pr2sw",
self.header.rdrq_packet_t)
self.rdrs_packet_sw2pr = self.input("rdrs_packet_sw2pr",
self.header.rdrs_packet_t)
# local variables
self.packet_w2e_wsti_d1 = self.var("packet_w2e_wsti_d1",
self.header.packet_t)
self.packet_e2w_esti_d1 = self.var("packet_e2w_esti_d1",
self.header.packet_t)
self.rdrs_packet_sw2pr_d1 = self.var("rdrs_packet_sw2pr_d1",
self.header.rdrs_packet_t)
self.rdrq_packet_pr2sw_filtered = self.var(
"rdrq_packet_pr2sw_filtered", self.header.rdrq_packet_t)
self.rdrq_packet_pr2sw_muxed = self.var("rdrq_packet_pr2sw_muxed",
self.header.rdrq_packet_t)
self.wr_packet_pr2sw_filtered = self.var("wr_packet_pr2sw_filtered",
self.header.wr_packet_t)
self.wr_packet_pr2sw_muxed = self.var("wr_packet_pr2sw_muxed",
self.header.wr_packet_t)
# localparam
self.packet_addr_tile_sel_msb = _params.bank_addr_width + \
_params.bank_sel_addr_width + _params.tile_sel_addr_width - 1
self.packet_addr_tile_sel_lsb = _params.bank_addr_width + _params.bank_sel_addr_width
self.add_is_even_stmt()
self.add_always(self.packet_pipeline)
self.add_always(self.rdrs_packet_pipeline)
self.add_always(self.rq_assign)
self.add_always(self.rs_assign)
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_core_strm_router")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.clk_en = self.input("clk_en", 1)
self.reset = self.reset("reset")
self.glb_tile_id = self.input("glb_tile_id",
self._params.tile_sel_addr_width)
self.packet_w2e_wsti = self.input("packet_w2e_wsti",
self.header.packet_t)
self.packet_e2w_wsto = self.output("packet_e2w_wsto",
self.header.packet_t)
self.packet_e2w_esti = self.input("packet_e2w_esti",
self.header.packet_t)
self.packet_w2e_esto = self.output("packet_w2e_esto",
self.header.packet_t)
self.packet_sw2sr = self.input("packet_sw2sr", self.header.packet_t)
self.packet_sr2sw = self.output("packet_sr2sw", self.header.packet_t)
self.cfg_tile_connected_prev = self.input("cfg_tile_connected_prev", 1)
self.cfg_tile_connected_next = self.input("cfg_tile_connected_next", 1)
# local variables
self.packet_w2e_wsti_d1 = self.var("packet_w2e_wsti_d1",
self.header.packet_t)
self.packet_w2e_wsti_turned = self.var("packet_w2e_wsti_turned",
self.header.packet_t)
self.packet_w2e_wsti_turned_d1 = self.var("packet_w2e_wsti_turned_d1",
self.header.packet_t)
self.packet_e2w_esti_d1 = self.var("packet_e2w_esti_d1",
self.header.packet_t)
self.packet_e2w_esti_turned = self.var("packet_e2w_esti_turned",
self.header.packet_t)
self.packet_e2w_esti_turned_d1 = self.var("packet_e2w_esti_turned_d1",
self.header.packet_t)
self.packet_sw2sr_d1 = self.var("packet_sw2sr_d1",
self.header.packet_t)
# localparam
self.add_is_even_stmt()
self.add_always(self.packet_wst_logic)
self.add_always(self.packet_est_logic)
self.add_always(self.packet_pipeline)
self.add_always(self.packet_sw2sr_pipeline)
self.add_always(self.packet_switch)
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_tile_pcfg_switch")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.reset = self.reset("reset")
self.cfg_pcfg_dma_mode = self.input("cfg_pcfg_dma_mode", 1)
self.cgra_cfg_core2sw = self.input("cgra_cfg_core2sw",
self.header.cgra_cfg_t)
self.cgra_cfg_jtag_wsti = self.input("cgra_cfg_jtag_wsti",
self.header.cgra_cfg_t)
self.cgra_cfg_jtag_esto = self.output("cgra_cfg_jtag_esto",
self.header.cgra_cfg_t)
self.cgra_cfg_pcfg_wsti = self.input("cgra_cfg_pcfg_wsti",
self.header.cgra_cfg_t)
self.cgra_cfg_pcfg_esto = self.output("cgra_cfg_pcfg_esto",
self.header.cgra_cfg_t)
self.cgra_cfg_g2f = self.output("cgra_cfg_g2f",
self.header.cgra_cfg_t,
size=self._params.cgra_per_glb,
packed=True)
self.cgra_cfg_jtag_wsti_rd_en_bypass = self.input(
"cgra_cfg_jtag_wsti_rd_en_bypass", 1)
self.cgra_cfg_jtag_wsti_addr_bypass = self.input(
"cgra_cfg_jtag_wsti_addr_bypass", self._params.cgra_cfg_addr_width)
self.cgra_cfg_jtag_esto_rd_en_bypass = self.output(
"cgra_cfg_jtag_esto_rd_en_bypass", 1)
self.cgra_cfg_jtag_esto_addr_bypass = self.output(
"cgra_cfg_jtag_esto_addr_bypass", self._params.cgra_cfg_addr_width)
# local variables
self.cgra_cfg_g2f_w = self.var("cgra_cfg_g2f_w",
self.header.cgra_cfg_t,
size=self._params.cgra_per_glb)
self.cgra_cfg_pcfg_muxed = self.var("cgra_cfg_pcfg_muxed",
self.header.cgra_cfg_t)
self.add_always(self.bypass_logic)
self.add_always(self.cgra_cfg_pcfg_muxed_logic)
self.add_always(self.pipeline)
# FIXME: Kratos does not support indexing for struct array yet
for i in range(self._params.cgra_per_glb):
self.add_always(self.cgra_cfg_g2f_logic, i=i)
self.add_always(self.pipeline_cgra_cfg_g2f)
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_tile_cfg")
self._params = _params
self.header = GlbHeader(self._params)
cfg_ifc = GlbConfigInterface(addr_width=self._params.axi_addr_width, data_width=self._params.axi_data_width)
# ports
self.clk = self.clock("clk")
self.reset = self.reset("reset", is_async=True)
self.glb_tile_id = self.input("glb_tile_id", self._params.tile_sel_addr_width)
# config port
self.if_cfg_wst_s = self.interface(cfg_ifc.slave, "if_cfg_wst_s", is_port=True)
self.if_cfg_est_m = self.interface(cfg_ifc.master, "if_cfg_est_m", is_port=True)
# configuration register struct
# TODO: Can we have a pass for this configuration?
self.cfg_data_network = self.output("cfg_data_network", self.header.cfg_data_network_t)
self.cfg_pcfg_network = self.output("cfg_pcfg_network", self.header.cfg_pcfg_network_t)
# st dma
self.cfg_st_dma_ctrl = self.output("cfg_st_dma_ctrl", self.header.cfg_dma_ctrl_t)
self.cfg_st_dma_header = self.output("cfg_st_dma_header", self.header.cfg_dma_header_t,
size=self._params.queue_depth)
# ld dma
self.cfg_ld_dma_ctrl = self.output("cfg_ld_dma_ctrl", self.header.cfg_dma_ctrl_t)
self.cfg_ld_dma_header = self.output("cfg_ld_dma_header", self.header.cfg_dma_header_t,
size=self._params.queue_depth)
# pcfg dma
self.cfg_pcfg_dma_ctrl = self.output("cfg_pcfg_dma_ctrl", self.header.cfg_pcfg_dma_ctrl_t)
self.cfg_pcfg_dma_header = self.output("cfg_pcfg_dma_header", self.header.cfg_pcfg_dma_header_t)
self.glb_pio_wrapper = self.get_glb_pio_wrapper()
# TODO: Update axi_reg_addr_width
self.add_child("glb_pio", self.glb_pio_wrapper)
self.glb_tile_cfg_ctrl = GlbTileCfgCtrl(self._params)
self.add_child("glb_tile_cfg_ctrl", self.glb_tile_cfg_ctrl)
self.wire_config_signals()
self.wire_ctrl_signals()
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_core_sram_cfg_ctrl")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.reset = self.reset("reset")
self.glb_tile_id = self.input(
"glb_tile_id", self._params.tile_sel_addr_width)
self.sram_cfg_ifc = GlbConfigInterface(
addr_width=self._params.glb_addr_width, data_width=self._params.axi_data_width)
self.bank_cfg_ifc = GlbConfigInterface(
addr_width=self._params.bank_addr_width, data_width=self._params.axi_data_width)
# config port
self.if_sram_cfg_est_m = self.interface(
self.sram_cfg_ifc.master, "if_sram_cfg_est_m", is_port=True)
self.if_sram_cfg_wst_s = self.interface(
self.sram_cfg_ifc.slave, "if_sram_cfg_wst_s", is_port=True)
# bank_config port
self.if_sram_cfg_core2bank_m = []
for i in range(self._params.banks_per_tile):
self.if_sram_cfg_core2bank_m.append(self.interface(
self.bank_cfg_ifc.master, f"if_sram_cfg_core2bank_m_{i}", is_port=True))
self.tile_id_match = self.var("tile_id_match", 1)
self.bank2core_rd_data_valid_w = self.var(
"bank2core_rd_data_valid_w", 1, size=self._params.banks_per_tile)
self.bank2core_rd_data_w = self.var(
"bank2core_rd_data_w", self._params.axi_data_width, size=self._params.banks_per_tile)
self.rd_data_valid_w = self.var("rd_data_valid_w", 1)
self.rd_data_w = self.var("rd_data_w", self._params.axi_data_width)
self.add_always(self.tile_id_match_logic)
for i in range(self._params.banks_per_tile):
self.add_always(self.if_sram_cfg_core2bank_logic, i=i)
self.add_always(self.rd_data_mux)
self.add_always(self.sram_cfg_pipeline)
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_bank")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.reset = self.reset("reset")
self.wr_packet = self.input(
"wr_packet", self.header.wr_packet_t)
self.rdrq_packet = self.input(
"rdrq_packet", self.header.rdrq_packet_t)
self.rdrs_packet = self.output(
"rdrs_packet", self.header.rdrs_packet_t)
self.bank_cfg_ifc = GlbConfigInterface(
addr_width=self._params.bank_addr_width, data_width=self._params.axi_data_width)
self.if_sram_cfg_s = self.interface(
self.bank_cfg_ifc.slave, f"if_sram_cfg_s", is_port=True)
# local variables
self.mem_rd_en = self.var("mem_rd_en", 1)
self.mem_wr_en = self.var("mem_wr_en", 1)
self.mem_addr = self.var("mem_addr", self._params.bank_addr_width)
self.mem_data_in = self.var(
"mem_data_in", self._params.bank_data_width)
self.mem_data_in_bit_sel = self.var(
"mem_data_in_bit_sel", self._params.bank_data_width)
self.mem_data_out = self.var(
"mem_data_out", self._params.bank_data_width)
# memory core declaration
self.wr_data_bit_sel = self.var(
"wr_data_bit_sel", self._params.bank_data_width)
self.wr_data_bit_sel_logic()
self.add_glb_bank_ctrl()
self.add_glb_bank_memory()
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_core_pcfg_dma")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.reset = self.reset("reset")
self.cgra_cfg_pcfg = self.output(
"cgra_cfg_pcfg", self.header.cgra_cfg_t)
self.rdrq_packet = self.output(
"rdrq_packet", self.header.rdrq_packet_t)
self.rdrs_packet = self.input("rdrs_packet", self.header.rdrs_packet_t)
self.cfg_pcfg_dma_ctrl_mode = self.input("cfg_pcfg_dma_ctrl_mode", 1)
self.cfg_pcfg_dma_header = self.input(
"cfg_pcfg_dma_header", self.header.cfg_pcfg_dma_header_t)
self.cfg_pcfg_network_latency = self.input(
"cfg_pcfg_network_latency", self._params.latency_width)
self.pcfg_start_pulse = self.input("pcfg_start_pulse", 1)
self.pcfg_done_pulse = self.output("pcfg_done_pulse", 1)
# localparam
self.bank_data_byte_offset = math.ceil(
self._params.bank_data_width / 8)
self.default_latency = (self._params.glb_switch_pipeline_depth
+ self._params.glb_bank_memory_pipeline_depth
+ self._params.sram_gen_pipeline_depth
+ self._params.sram_gen_output_pipeline_depth
+ 1 # SRAM macro read latency
+ self._params.glb_switch_pipeline_depth
+ 2 # FIXME: Unnecessary delay of moving back and forth btw switch and router
+ 1 # dma cache register delay
)
# local variables
self.is_running_r = self.var("is_running_r", 1)
self.start_pulse_r = self.var("start_pulse_r", 1)
self.done_pulse_r = self.var("done_pulse_r", 1)
self.num_cfg_cnt_r = self.var(
"num_cfg_cnt_r", self._params.max_num_cfg_width)
self.num_cfg_cnt_next = self.var(
"num_cfg_cnt_next", self._params.max_num_cfg_width)
self.addr_r = self.var("addr_r", self._params.glb_addr_width)
self.addr_next = self.var("addr_next", self._params.glb_addr_width)
self.rdrq_packet_rd_en_r = self.var("rdrq_packet_rd_en_r", 1)
self.rdrq_packet_rd_en_next = self.var("rdrq_packet_rd_en_next", 1)
self.rdrq_packet_rd_addr_r = self.var(
"rdrq_packet_rd_addr_r", self._params.glb_addr_width)
self.rdrq_packet_rd_addr_next = self.var(
"rdrq_packet_rd_addr_next", self._params.glb_addr_width)
self.rdrs_packet_rd_data_r = self.var(
"rdrs_packet_rd_data_r", self._params.bank_data_width)
self.rdrs_packet_rd_data_valid_r = self.var(
"rdrs_packet_rd_data_valid_r", 1)
# Add always statements
self.add_always(self.start_pulse_ff)
self.add_always(self.done_pulse_ff)
self.add_always(self.is_running_ff)
self.add_always(self.adgn_logic)
self.add_always(self.adgn_ff)
self.add_always(self.rdrq_packet_logic)
self.add_always(self.rdrq_packet_ff)
self.add_always(self.rdrs_packet_ff)
self.assign_rdrq_packet()
self.assign_cgra_cfg_output()
self.add_pcfg_dma_done_pulse_pipeline()
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_tile")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.clk_en = self.clock_en("clk_en")
self.reset = self.reset("reset")
self.glb_tile_id = self.input("glb_tile_id",
self._params.tile_sel_addr_width)
self.proc_wr_en_e2w_esti = self.input("proc_wr_en_e2w_esti", 1)
self.proc_wr_strb_e2w_esti = self.input(
"proc_wr_strb_e2w_esti", self._params.bank_data_width // 8)
self.proc_wr_addr_e2w_esti = self.input("proc_wr_addr_e2w_esti",
self._params.glb_addr_width)
self.proc_wr_data_e2w_esti = self.input("proc_wr_data_e2w_esti",
self._params.bank_data_width)
self.proc_rd_en_e2w_esti = self.input("proc_rd_en_e2w_esti", 1)
self.proc_rd_addr_e2w_esti = self.input("proc_rd_addr_e2w_esti",
self._params.glb_addr_width)
self.proc_rd_data_e2w_esti = self.input("proc_rd_data_e2w_esti",
self._params.bank_data_width)
self.proc_rd_data_valid_e2w_esti = self.input(
"proc_rd_data_valid_e2w_esti", 1)
self.proc_wr_en_w2e_esto = self.output("proc_wr_en_w2e_esto", 1)
self.proc_wr_strb_w2e_esto = self.output(
"proc_wr_strb_w2e_esto", self._params.bank_data_width // 8)
self.proc_wr_addr_w2e_esto = self.output("proc_wr_addr_w2e_esto",
self._params.glb_addr_width)
self.proc_wr_data_w2e_esto = self.output("proc_wr_data_w2e_esto",
self._params.bank_data_width)
self.proc_rd_en_w2e_esto = self.output("proc_rd_en_w2e_esto", 1)
self.proc_rd_addr_w2e_esto = self.output("proc_rd_addr_w2e_esto",
self._params.glb_addr_width)
self.proc_rd_data_w2e_esto = self.output("proc_rd_data_w2e_esto",
self._params.bank_data_width)
self.proc_rd_data_valid_w2e_esto = self.output(
"proc_rd_data_valid_w2e_esto", 1)
self.proc_wr_en_w2e_wsti = self.input("proc_wr_en_w2e_wsti", 1)
self.proc_wr_strb_w2e_wsti = self.input(
"proc_wr_strb_w2e_wsti", self._params.bank_data_width // 8)
self.proc_wr_addr_w2e_wsti = self.input("proc_wr_addr_w2e_wsti",
self._params.glb_addr_width)
self.proc_wr_data_w2e_wsti = self.input("proc_wr_data_w2e_wsti",
self._params.bank_data_width)
self.proc_rd_en_w2e_wsti = self.input("proc_rd_en_w2e_wsti", 1)
self.proc_rd_addr_w2e_wsti = self.input("proc_rd_addr_w2e_wsti",
self._params.glb_addr_width)
self.proc_rd_data_w2e_wsti = self.input("proc_rd_data_w2e_wsti",
self._params.bank_data_width)
self.proc_rd_data_valid_w2e_wsti = self.input(
"proc_rd_data_valid_w2e_wsti", 1)
self.proc_wr_en_e2w_wsto = self.output("proc_wr_en_e2w_wsto", 1)
self.proc_wr_strb_e2w_wsto = self.output(
"proc_wr_strb_e2w_wsto", self._params.bank_data_width // 8)
self.proc_wr_addr_e2w_wsto = self.output("proc_wr_addr_e2w_wsto",
self._params.glb_addr_width)
self.proc_wr_data_e2w_wsto = self.output("proc_wr_data_e2w_wsto",
self._params.bank_data_width)
self.proc_rd_en_e2w_wsto = self.output("proc_rd_en_e2w_wsto", 1)
self.proc_rd_addr_e2w_wsto = self.output("proc_rd_addr_e2w_wsto",
self._params.glb_addr_width)
self.proc_rd_data_e2w_wsto = self.output("proc_rd_data_e2w_wsto",
self._params.bank_data_width)
self.proc_rd_data_valid_e2w_wsto = self.output(
"proc_rd_data_valid_e2w_wsto", 1)
self.strm_wr_en_e2w_esti = self.input("strm_wr_en_e2w_esti", 1)
self.strm_wr_strb_e2w_esti = self.input(
"strm_wr_strb_e2w_esti", self._params.bank_data_width // 8)
self.strm_wr_addr_e2w_esti = self.input("strm_wr_addr_e2w_esti",
self._params.glb_addr_width)
self.strm_wr_data_e2w_esti = self.input("strm_wr_data_e2w_esti",
self._params.bank_data_width)
self.strm_rd_en_e2w_esti = self.input("strm_rd_en_e2w_esti", 1)
self.strm_rd_addr_e2w_esti = self.input("strm_rd_addr_e2w_esti",
self._params.glb_addr_width)
self.strm_rd_data_e2w_esti = self.input("strm_rd_data_e2w_esti",
self._params.bank_data_width)
self.strm_rd_data_valid_e2w_esti = self.input(
"strm_rd_data_valid_e2w_esti", 1)
self.strm_wr_en_w2e_esto = self.output("strm_wr_en_w2e_esto", 1)
self.strm_wr_strb_w2e_esto = self.output(
"strm_wr_strb_w2e_esto", self._params.bank_data_width // 8)
self.strm_wr_addr_w2e_esto = self.output("strm_wr_addr_w2e_esto",
self._params.glb_addr_width)
self.strm_wr_data_w2e_esto = self.output("strm_wr_data_w2e_esto",
self._params.bank_data_width)
self.strm_rd_en_w2e_esto = self.output("strm_rd_en_w2e_esto", 1)
self.strm_rd_addr_w2e_esto = self.output("strm_rd_addr_w2e_esto",
self._params.glb_addr_width)
self.strm_rd_data_w2e_esto = self.output("strm_rd_data_w2e_esto",
self._params.bank_data_width)
self.strm_rd_data_valid_w2e_esto = self.output(
"strm_rd_data_valid_w2e_esto", 1)
self.strm_wr_en_w2e_wsti = self.input("strm_wr_en_w2e_wsti", 1)
self.strm_wr_strb_w2e_wsti = self.input(
"strm_wr_strb_w2e_wsti", self._params.bank_data_width // 8)
self.strm_wr_addr_w2e_wsti = self.input("strm_wr_addr_w2e_wsti",
self._params.glb_addr_width)
self.strm_wr_data_w2e_wsti = self.input("strm_wr_data_w2e_wsti",
self._params.bank_data_width)
self.strm_rd_en_w2e_wsti = self.input("strm_rd_en_w2e_wsti", 1)
self.strm_rd_addr_w2e_wsti = self.input("strm_rd_addr_w2e_wsti",
self._params.glb_addr_width)
self.strm_rd_data_w2e_wsti = self.input("strm_rd_data_w2e_wsti",
self._params.bank_data_width)
self.strm_rd_data_valid_w2e_wsti = self.input(
"strm_rd_data_valid_w2e_wsti", 1)
self.strm_wr_en_e2w_wsto = self.output("strm_wr_en_e2w_wsto", 1)
self.strm_wr_strb_e2w_wsto = self.output(
"strm_wr_strb_e2w_wsto", self._params.bank_data_width // 8)
self.strm_wr_addr_e2w_wsto = self.output("strm_wr_addr_e2w_wsto",
self._params.glb_addr_width)
self.strm_wr_data_e2w_wsto = self.output("strm_wr_data_e2w_wsto",
self._params.bank_data_width)
self.strm_rd_en_e2w_wsto = self.output("strm_rd_en_e2w_wsto", 1)
self.strm_rd_addr_e2w_wsto = self.output("strm_rd_addr_e2w_wsto",
self._params.glb_addr_width)
self.strm_rd_data_e2w_wsto = self.output("strm_rd_data_e2w_wsto",
self._params.bank_data_width)
self.strm_rd_data_valid_e2w_wsto = self.output(
"strm_rd_data_valid_e2w_wsto", 1)
self.pcfg_rd_en_e2w_esti = self.input("pcfg_rd_en_e2w_esti", 1)
self.pcfg_rd_addr_e2w_esti = self.input("pcfg_rd_addr_e2w_esti",
self._params.glb_addr_width)
self.pcfg_rd_data_e2w_esti = self.input("pcfg_rd_data_e2w_esti",
self._params.bank_data_width)
self.pcfg_rd_data_valid_e2w_esti = self.input(
"pcfg_rd_data_valid_e2w_esti", 1)
self.pcfg_rd_en_w2e_esto = self.output("pcfg_rd_en_w2e_esto", 1)
self.pcfg_rd_addr_w2e_esto = self.output("pcfg_rd_addr_w2e_esto",
self._params.glb_addr_width)
self.pcfg_rd_data_w2e_esto = self.output("pcfg_rd_data_w2e_esto",
self._params.bank_data_width)
self.pcfg_rd_data_valid_w2e_esto = self.output(
"pcfg_rd_data_valid_w2e_esto", 1)
self.pcfg_rd_en_w2e_wsti = self.input("pcfg_rd_en_w2e_wsti", 1)
self.pcfg_rd_addr_w2e_wsti = self.input("pcfg_rd_addr_w2e_wsti",
self._params.glb_addr_width)
self.pcfg_rd_data_w2e_wsti = self.input("pcfg_rd_data_w2e_wsti",
self._params.bank_data_width)
self.pcfg_rd_data_valid_w2e_wsti = self.input(
"pcfg_rd_data_valid_w2e_wsti", 1)
self.pcfg_rd_en_e2w_wsto = self.output("pcfg_rd_en_e2w_wsto", 1)
self.pcfg_rd_addr_e2w_wsto = self.output("pcfg_rd_addr_e2w_wsto",
self._params.glb_addr_width)
self.pcfg_rd_data_e2w_wsto = self.output("pcfg_rd_data_e2w_wsto",
self._params.bank_data_width)
self.pcfg_rd_data_valid_e2w_wsto = self.output(
"pcfg_rd_data_valid_e2w_wsto", 1)
self.if_cfg_est_m_wr_en = self.output("if_cfg_est_m_wr_en", 1)
self.if_cfg_est_m_wr_addr = self.output("if_cfg_est_m_wr_addr",
self._params.axi_addr_width)
self.if_cfg_est_m_wr_data = self.output("if_cfg_est_m_wr_data",
self._params.axi_data_width)
self.if_cfg_est_m_rd_en = self.output("if_cfg_est_m_rd_en", 1)
self.if_cfg_est_m_rd_addr = self.output("if_cfg_est_m_rd_addr",
self._params.axi_addr_width)
self.if_cfg_est_m_rd_data = self.input("if_cfg_est_m_rd_data",
self._params.axi_data_width)
self.if_cfg_est_m_rd_data_valid = self.input(
"if_cfg_est_m_rd_data_valid", 1)
self.if_cfg_wst_s_wr_en = self.input("if_cfg_wst_s_wr_en", 1)
self.if_cfg_wst_s_wr_addr = self.input("if_cfg_wst_s_wr_addr",
self._params.axi_addr_width)
self.if_cfg_wst_s_wr_data = self.input("if_cfg_wst_s_wr_data",
self._params.axi_data_width)
self.if_cfg_wst_s_rd_en = self.input("if_cfg_wst_s_rd_en", 1)
self.if_cfg_wst_s_rd_addr = self.input("if_cfg_wst_s_rd_addr",
self._params.axi_addr_width)
self.if_cfg_wst_s_rd_data = self.output("if_cfg_wst_s_rd_data",
self._params.axi_data_width)
self.if_cfg_wst_s_rd_data_valid = self.output(
"if_cfg_wst_s_rd_data_valid", 1)
self.if_sram_cfg_est_m_wr_en = self.output("if_sram_cfg_est_m_wr_en",
1)
self.if_sram_cfg_est_m_wr_addr = self.output(
"if_sram_cfg_est_m_wr_addr", self._params.glb_addr_width)
self.if_sram_cfg_est_m_wr_data = self.output(
"if_sram_cfg_est_m_wr_data", self._params.axi_data_width)
self.if_sram_cfg_est_m_rd_en = self.output("if_sram_cfg_est_m_rd_en",
1)
self.if_sram_cfg_est_m_rd_addr = self.output(
"if_sram_cfg_est_m_rd_addr", self._params.glb_addr_width)
self.if_sram_cfg_est_m_rd_data = self.input(
"if_sram_cfg_est_m_rd_data", self._params.axi_data_width)
self.if_sram_cfg_est_m_rd_data_valid = self.input(
"if_sram_cfg_est_m_rd_data_valid", 1)
self.if_sram_cfg_wst_s_wr_en = self.input("if_sram_cfg_wst_s_wr_en", 1)
self.if_sram_cfg_wst_s_wr_addr = self.input(
"if_sram_cfg_wst_s_wr_addr", self._params.glb_addr_width)
self.if_sram_cfg_wst_s_wr_data = self.input(
"if_sram_cfg_wst_s_wr_data", self._params.axi_data_width)
self.if_sram_cfg_wst_s_rd_en = self.input("if_sram_cfg_wst_s_rd_en", 1)
self.if_sram_cfg_wst_s_rd_addr = self.input(
"if_sram_cfg_wst_s_rd_addr", self._params.glb_addr_width)
self.if_sram_cfg_wst_s_rd_data = self.output(
"if_sram_cfg_wst_s_rd_data", self._params.axi_data_width)
self.if_sram_cfg_wst_s_rd_data_valid = self.output(
"if_sram_cfg_wst_s_rd_data_valid", 1)
self.cfg_tile_connected_wsti = self.input("cfg_tile_connected_wsti", 1)
self.cfg_tile_connected_esto = self.output("cfg_tile_connected_esto",
1)
self.cfg_pcfg_tile_connected_wsti = self.input(
"cfg_pcfg_tile_connected_wsti", 1)
self.cfg_pcfg_tile_connected_esto = self.output(
"cfg_pcfg_tile_connected_esto", 1)
self.cgra_cfg_jtag_wsti_wr_en = self.input("cgra_cfg_jtag_wsti_wr_en",
1)
self.cgra_cfg_jtag_wsti_rd_en = self.input("cgra_cfg_jtag_wsti_rd_en",
1)
self.cgra_cfg_jtag_wsti_addr = self.input(
"cgra_cfg_jtag_wsti_addr", self._params.cgra_cfg_addr_width)
self.cgra_cfg_jtag_wsti_data = self.input(
"cgra_cfg_jtag_wsti_data", self._params.cgra_cfg_data_width)
self.cgra_cfg_jtag_esto_wr_en = self.output("cgra_cfg_jtag_esto_wr_en",
1)
self.cgra_cfg_jtag_esto_rd_en = self.output("cgra_cfg_jtag_esto_rd_en",
1)
self.cgra_cfg_jtag_esto_addr = self.output(
"cgra_cfg_jtag_esto_addr", self._params.cgra_cfg_addr_width)
self.cgra_cfg_jtag_esto_data = self.output(
"cgra_cfg_jtag_esto_data", self._params.cgra_cfg_data_width)
self.cgra_cfg_jtag_wsti_rd_en_bypass = self.input(
"cgra_cfg_jtag_wsti_rd_en_bypass", 1)
self.cgra_cfg_jtag_wsti_addr_bypass = self.input(
"cgra_cfg_jtag_wsti_addr_bypass", self._params.cgra_cfg_addr_width)
self.cgra_cfg_jtag_esto_rd_en_bypass = self.output(
"cgra_cfg_jtag_esto_rd_en_bypass", 1)
self.cgra_cfg_jtag_esto_addr_bypass = self.output(
"cgra_cfg_jtag_esto_addr_bypass", self._params.cgra_cfg_addr_width)
self.cgra_cfg_pcfg_wsti_wr_en = self.input("cgra_cfg_pcfg_wsti_wr_en",
1)
self.cgra_cfg_pcfg_wsti_rd_en = self.input("cgra_cfg_pcfg_wsti_rd_en",
1)
self.cgra_cfg_pcfg_wsti_addr = self.input(
"cgra_cfg_pcfg_wsti_addr", self._params.cgra_cfg_addr_width)
self.cgra_cfg_pcfg_wsti_data = self.input(
"cgra_cfg_pcfg_wsti_data", self._params.cgra_cfg_data_width)
self.cgra_cfg_pcfg_esto_wr_en = self.output("cgra_cfg_pcfg_esto_wr_en",
1)
self.cgra_cfg_pcfg_esto_rd_en = self.output("cgra_cfg_pcfg_esto_rd_en",
1)
self.cgra_cfg_pcfg_esto_addr = self.output(
"cgra_cfg_pcfg_esto_addr", self._params.cgra_cfg_addr_width)
self.cgra_cfg_pcfg_esto_data = self.output(
"cgra_cfg_pcfg_esto_data", self._params.cgra_cfg_data_width)
self.stream_data_f2g = self.input("stream_data_f2g",
self._params.cgra_data_width,
size=self._params.cgra_per_glb,
packed=True)
self.stream_data_valid_f2g = self.input("stream_data_valid_f2g",
1,
size=self._params.cgra_per_glb,
packed=True)
self.stream_data_g2f = self.output("stream_data_g2f",
self._params.cgra_data_width,
size=self._params.cgra_per_glb,
packed=True)
self.stream_data_valid_g2f = self.output(
"stream_data_valid_g2f",
1,
size=self._params.cgra_per_glb,
packed=True)
self.cgra_cfg_g2f_cfg_wr_en = self.output(
"cgra_cfg_g2f_cfg_wr_en",
1,
size=self._params.cgra_per_glb,
packed=True)
self.cgra_cfg_g2f_cfg_rd_en = self.output(
"cgra_cfg_g2f_cfg_rd_en",
1,
size=self._params.cgra_per_glb,
packed=True)
self.cgra_cfg_g2f_cfg_addr = self.output(
"cgra_cfg_g2f_cfg_addr",
self._params.cgra_cfg_addr_width,
size=self._params.cgra_per_glb,
packed=True)
self.cgra_cfg_g2f_cfg_data = self.output(
"cgra_cfg_g2f_cfg_data",
self._params.cgra_cfg_data_width,
size=self._params.cgra_per_glb,
packed=True)
self.strm_g2f_start_pulse = self.input("strm_g2f_start_pulse", 1)
self.strm_f2g_start_pulse = self.input("strm_f2g_start_pulse", 1)
self.pcfg_start_pulse = self.input("pcfg_start_pulse", 1)
self.strm_f2g_interrupt_pulse = self.output("strm_f2g_interrupt_pulse",
1)
self.strm_g2f_interrupt_pulse = self.output("strm_g2f_interrupt_pulse",
1)
self.pcfg_g2f_interrupt_pulse = self.output("pcfg_g2f_interrupt_pulse",
1)
self.if_cfg = GlbConfigInterface(
addr_width=self._params.axi_addr_width,
data_width=self._params.axi_data_width)
self.if_sram_cfg = GlbConfigInterface(
addr_width=self._params.glb_addr_width,
data_width=self._params.axi_data_width)
self.if_cfg_est_m = self.interface(self.if_cfg, "if_cfg_est_m")
self.if_cfg_wst_s = self.interface(self.if_cfg, "if_cfg_wst_s")
self.if_sram_cfg_est_m = self.interface(self.if_sram_cfg,
"if_sram_cfg_est_m")
self.if_sram_cfg_wst_s = self.interface(self.if_sram_cfg,
"if_sram_cfg_wst_s")
self.glb_tile_cfg = GlbTileCfg(_params=self._params)
self.add_child("glb_tile_cfg",
self.glb_tile_cfg,
clk=self.clk,
reset=self.reset,
glb_tile_id=self.glb_tile_id)
self.glb_tile_pcfg_switch = GlbTilePcfgSwitch(_params=self._params)
self.add_child("glb_tile_pcfg_switch",
self.glb_tile_pcfg_switch,
clk=self.clk,
reset=self.reset)
self.glb_core = GlbCore(_params=self._params)
self.add_child("glb_core",
self.glb_core,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
glb_tile_id=self.glb_tile_id)
if self._params.is_sram_stub:
self.readmemh_block = RawStringStmt([
"initial begin",
"\tstring b0_file_name;",
"\tstring b1_file_name;",
"\tstring load_arg;",
"\t$sformat(b0_file_name, \"testvectors/tile%0d_b0.dat\", glb_tile_id);",
"\t$sformat(b1_file_name, \"testvectors/tile%0d_b1.dat\", glb_tile_id);",
"\t$sformat(load_arg, \"LOAD%0d\", glb_tile_id);",
"\tif (($test$plusargs(load_arg))) begin",
"\t\t$readmemh(b0_file_name, glb_core.glb_bank_0.glb_bank_memory.glb_bank_sram_stub.mem);", # noqa
"\t\t$readmemh(b1_file_name, glb_core.glb_bank_1.glb_bank_memory.glb_bank_sram_stub.mem);", # noqa
"\tend",
"end"
])
self.writememh_block = RawStringStmt([
"final begin",
"\tstring b0_file_name;",
"\tstring b1_file_name;",
"\tstring save_arg;",
"\t$sformat(b0_file_name, \"testvectors/tile%0d_b0_out.dat\", glb_tile_id);",
"\t$sformat(b1_file_name, \"testvectors/tile%0d_b1_out.dat\", glb_tile_id);",
"\t$sformat(save_arg, \"SAVE%0d\", glb_tile_id);",
"\tif (($test$plusargs(save_arg))) begin",
"\t\t$writememh(b0_file_name, glb_core.glb_bank_0.glb_bank_memory.glb_bank_sram_stub.mem);", # noqa
"\t\t$writememh(b1_file_name, glb_core.glb_bank_1.glb_bank_memory.glb_bank_sram_stub.mem);", # noqa
"\tend",
"end"
])
self.add_stmt(self.readmemh_block.stmt())
self.add_stmt(self.writememh_block.stmt())
self.interface_wiring()
self.tile2cfg_wiring()
self.tile2core_wiring()
self.tile2pcfgs_wiring()
self.cfg2core_wiring()
self.core2pcfgs_wiring()
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_core_load_dma")
self._params = _params
self.header = GlbHeader(self._params)
assert self._params.bank_data_width == self._params.cgra_data_width * 4
self.clk = self.clock("clk")
self.clk_en = self.clock_en("clk_en")
self.reset = self.reset("reset")
self.data_g2f = self.output("data_g2f",
width=self._params.cgra_data_width)
self.data_valid_g2f = self.output("data_valid_g2f", width=1)
self.rdrq_packet = self.output("rdrq_packet",
self.header.rdrq_packet_t)
self.rdrs_packet = self.input("rdrs_packet", self.header.rdrs_packet_t)
self.cfg_ld_dma_num_repeat = self.input(
"cfg_ld_dma_num_repeat",
clog2(self._params.queue_depth) + 1)
self.cfg_ld_dma_ctrl_use_valid = self.input(
"cfg_ld_dma_ctrl_use_valid", 1)
self.cfg_ld_dma_ctrl_mode = self.input("cfg_ld_dma_ctrl_mode", 2)
self.cfg_data_network_latency = self.input("cfg_data_network_latency",
self._params.latency_width)
self.cfg_ld_dma_header = self.input("cfg_ld_dma_header",
self.header.cfg_dma_header_t,
size=self._params.queue_depth)
self.ld_dma_start_pulse = self.input("ld_dma_start_pulse", 1)
self.ld_dma_done_pulse = self.output("ld_dma_done_pulse", 1)
# local parameter
self.default_latency = (
self._params.glb_switch_pipeline_depth +
self._params.glb_bank_memory_pipeline_depth +
self._params.sram_gen_pipeline_depth +
self._params.sram_gen_output_pipeline_depth +
1 # SRAM macro read latency
+ self._params.glb_switch_pipeline_depth +
2 # FIXME: Unnecessary delay of moving back and forth btw switch and router
+ 1 # load_dma cache register delay
)
# local variables
self.strm_data = self.var("strm_data", self._params.cgra_data_width)
self.strm_data_r = self.var("strm_data_r",
self._params.cgra_data_width)
self.strm_data_valid = self.var("strm_data_valid", 1)
self.strm_data_valid_r = self.var("strm_data_valid_r", 1)
self.strm_data_sel = self.var(
"strm_data_sel",
self._params.bank_byte_offset - self._params.cgra_byte_offset)
self.strm_rd_en_w = self.var("strm_rd_en_w", 1)
self.strm_rd_addr_w = self.var("strm_rd_addr_w",
self._params.glb_addr_width)
self.last_strm_rd_addr_r = self.var("last_strm_rd_addr_r",
self._params.glb_addr_width)
self.ld_dma_start_pulse_next = self.var("ld_dma_start_pulse_next", 1)
self.ld_dma_start_pulse_r = self.var("ld_dma_start_pulse_r", 1)
self.is_first = self.var("is_first", 1)
self.ld_dma_done_pulse_w = self.var("ld_dma_done_pulse_w", 1)
self.bank_addr_match = self.var("bank_addr_match", 1)
self.bank_rdrq_rd_en = self.var("bank_rdrq_rd_en", 1)
self.bank_rdrq_rd_addr = self.var("bank_rdrq_rd_addr",
self._params.glb_addr_width)
self.bank_rdrs_data_cache_r = self.var("bank_rdrs_data_cache_r",
self._params.bank_data_width)
self.strm_run = self.var("strm_run", 1)
self.loop_done = self.var("loop_done", 1)
self.cycle_valid = self.var("cycle_valid", 1)
self.cycle_count = self.var("cycle_count", self._params.axi_data_width)
self.cycle_current_addr = self.var("cycle_current_addr",
self._params.axi_data_width)
self.data_current_addr = self.var("data_current_addr",
self._params.axi_data_width)
self.loop_mux_sel = self.var("loop_mux_sel",
clog2(self._params.loop_level))
self.repeat_cnt = self.var("repeat_cnt",
clog2(self._params.queue_depth) + 1)
if self._params.queue_depth != 1:
self.queue_sel_r = self.var("queue_sel_r",
max(1, clog2(self.repeat_cnt.width)))
# Current dma header
self.current_dma_header = self.var("current_dma_header",
self.header.cfg_dma_header_t)
if self._params.queue_depth == 1:
self.wire(self.cfg_ld_dma_header, self.current_dma_header)
else:
self.wire(self.cfg_ld_dma_header[self.queue_sel_r],
self.current_dma_header)
if self._params.queue_depth != 1:
self.add_always(self.queue_sel_ff)
self.add_always(self.repeat_cnt_ff)
self.add_always(self.cycle_counter)
self.add_always(self.is_first_ff)
self.add_always(self.strm_run_ff)
self.add_always(self.strm_data_ff)
self.add_strm_data_start_pulse_pipeline()
self.add_ld_dma_done_pulse_pipeline()
self.add_strm_rd_en_pipeline()
self.add_strm_rd_addr_pipeline()
self.add_always(self.ld_dma_start_pulse_logic)
self.add_always(self.ld_dma_start_pulse_ff)
self.add_always(self.strm_data_mux)
self.add_always(self.ld_dma_done_pulse_logic)
self.add_always(self.strm_rdrq_packet_ff)
self.add_always(self.last_strm_rd_addr_ff)
self.add_always(self.bank_rdrq_packet_logic)
self.add_always(self.bank_rdrs_data_cache_ff)
self.add_always(self.strm_data_logic)
# Loop iteration shared for cycle and data
self.loop_iter = GlbLoopIter(self._params)
self.add_child("loop_iter",
self.loop_iter,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
step=self.cycle_valid,
mux_sel_out=self.loop_mux_sel,
restart=self.loop_done)
self.wire(self.loop_iter.dim, self.current_dma_header[f"dim"])
for i in range(self._params.loop_level):
self.wire(self.loop_iter.ranges[i],
self.current_dma_header[f"range_{i}"])
# Cycle stride
self.cycle_stride_sched_gen = GlbSchedGen(self._params)
self.add_child("cycle_stride_sched_gen",
self.cycle_stride_sched_gen,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
restart=self.ld_dma_start_pulse_r,
cycle_count=self.cycle_count,
current_addr=self.cycle_current_addr,
finished=self.loop_done,
valid_output=self.cycle_valid)
self.cycle_stride_addr_gen = GlbAddrGen(self._params)
self.add_child("cycle_stride_addr_gen",
self.cycle_stride_addr_gen,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
restart=self.ld_dma_start_pulse_r,
step=self.cycle_valid,
mux_sel=self.loop_mux_sel,
addr_out=self.cycle_current_addr)
self.wire(
self.cycle_stride_addr_gen.start_addr,
ext(self.current_dma_header[f"cycle_start_addr"],
self._params.axi_data_width))
for i in range(self._params.loop_level):
self.wire(self.cycle_stride_addr_gen.strides[i],
self.current_dma_header[f"cycle_stride_{i}"])
# Data stride
self.data_stride_addr_gen = GlbAddrGen(self._params)
self.add_child("data_stride_addr_gen",
self.data_stride_addr_gen,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
restart=self.ld_dma_start_pulse_r,
step=self.cycle_valid,
mux_sel=self.loop_mux_sel,
addr_out=self.data_current_addr)
self.wire(
self.data_stride_addr_gen.start_addr,
ext(self.current_dma_header[f"start_addr"],
self._params.axi_data_width))
for i in range(self._params.loop_level):
self.wire(self.data_stride_addr_gen.strides[i],
self.current_dma_header[f"stride_{i}"])
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_core_store_dma")
self._params = _params
self.header = GlbHeader(self._params)
assert self._params.bank_data_width == self._params.cgra_data_width * 4
self.clk = self.clock("clk")
self.clk_en = self.clock_en("clk_en")
self.reset = self.reset("reset")
self.data_f2g = self.input(
"data_f2g", width=self._params.cgra_data_width)
self.data_valid_f2g = self.input("data_valid_f2g", width=1)
self.wr_packet = self.output(
"wr_packet", self.header.wr_packet_t)
self.cfg_st_dma_num_repeat = self.input("cfg_st_dma_num_repeat", clog2(self._params.queue_depth) + 1)
self.cfg_st_dma_ctrl_mode = self.input("cfg_st_dma_ctrl_mode", 2)
self.cfg_st_dma_ctrl_use_valid = self.input("cfg_st_dma_ctrl_use_valid", 1)
self.cfg_data_network_latency = self.input(
"cfg_data_network_latency", self._params.latency_width)
self.cfg_st_dma_header = self.input(
"cfg_st_dma_header", self.header.cfg_dma_header_t, size=self._params.queue_depth, explicit_array=True)
self.st_dma_start_pulse = self.input("st_dma_start_pulse", 1)
self.st_dma_done_pulse = self.output("st_dma_done_pulse", 1)
# localparam
self.default_latency = (self._params.glb_bank_memory_pipeline_depth
+ self._params.sram_gen_pipeline_depth
+ self._params.glb_switch_pipeline_depth
)
self.cgra_strb_width = self._params.cgra_data_width // 8
self.cgra_strb_value = 2 ** (self._params.cgra_data_width // 8) - 1
# local variables
self.strm_wr_data_w = self.var("strm_wr_data_w", width=self._params.cgra_data_width)
self.strm_wr_addr_w = self.var("strm_wr_addr_w", width=self._params.glb_addr_width)
self.last_strm_wr_addr_r = self.var("last_strm_wr_addr_r", width=self._params.glb_addr_width)
self.strm_wr_en_w = self.var("strm_wr_en_w", width=1)
self.strm_data_sel = self.var("strm_data_sel", self._params.bank_byte_offset - self._params.cgra_byte_offset)
self.bank_addr_match = self.var("bank_addr_match", 1)
self.bank_wr_en = self.var("bank_wr_en", 1)
self.bank_wr_addr = self.var("bank_wr_addr", width=self._params.glb_addr_width)
self.bank_wr_data_cache_r = self.var("bank_wr_data_cache_r", self._params.bank_data_width)
self.bank_wr_data_cache_w = self.var("bank_wr_data_cache_w", self._params.bank_data_width)
self.bank_wr_strb_cache_r = self.var("bank_wr_strb_cache_r", math.ceil(self._params.bank_data_width / 8))
self.bank_wr_strb_cache_w = self.var("bank_wr_strb_cache_w", math.ceil(self._params.bank_data_width / 8))
self.done_pulse_w = self.var("done_pulse_w", 1)
self.st_dma_start_pulse_next = self.var("st_dma_start_pulse_next", 1)
self.st_dma_start_pulse_r = self.var("st_dma_start_pulse_r", 1)
self.is_first = self.var("is_first", 1)
self.is_last = self.var("is_last", 1)
self.strm_run = self.var("strm_run", 1)
self.loop_done = self.var("loop_done", 1)
self.cycle_valid = self.var("cycle_valid", 1)
self.cycle_valid_muxed = self.var("cycle_valid_muxed", 1)
self.cycle_count = self.var("cycle_count", self._params.axi_data_width)
self.cycle_current_addr = self.var("cycle_current_addr", self._params.axi_data_width)
self.data_current_addr = self.var("data_current_addr", self._params.axi_data_width)
self.loop_mux_sel = self.var("loop_mux_sel", clog2(self._params.loop_level))
self.repeat_cnt = self.var("repeat_cnt", clog2(self._params.queue_depth) + 1)
if self._params.queue_depth != 1:
self.queue_sel_r = self.var("queue_sel_r", max(1, clog2(self.repeat_cnt.width)))
# Current dma header
self.current_dma_header = self.var("current_dma_header", self.header.cfg_dma_header_t)
if self._params.queue_depth == 1:
self.wire(self.cfg_st_dma_header, self.current_dma_header)
else:
self.wire(self.cfg_st_dma_header[self.queue_sel_r], self.current_dma_header)
if self._params.queue_depth != 1:
self.add_always(self.queue_sel_ff)
self.add_always(self.repeat_cnt_ff)
self.add_always(self.is_first_ff)
self.add_always(self.is_last_ff)
self.add_always(self.strm_run_ff)
self.add_always(self.st_dma_start_pulse_logic)
self.add_always(self.st_dma_start_pulse_ff)
self.add_always(self.cycle_counter)
self.add_always(self.cycle_valid_comb)
self.add_always(self.strm_wr_packet_comb)
self.add_always(self.last_strm_wr_addr_ff)
self.add_always(self.strm_data_sel_comb)
self.add_always(self.bank_wr_packet_cache_comb)
self.add_always(self.bank_wr_packet_cache_ff)
self.add_always(self.bank_wr_packet_logic)
self.add_always(self.wr_packet_logic)
self.add_always(self.strm_done_pulse_logic)
self.add_done_pulse_pipeline()
# Loop iteration shared for cycle and data
self.loop_iter = GlbLoopIter(self._params)
self.add_child("loop_iter",
self.loop_iter,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
step=self.cycle_valid_muxed,
mux_sel_out=self.loop_mux_sel,
restart=self.loop_done)
self.wire(self.loop_iter.dim, self.current_dma_header[f"dim"])
for i in range(self._params.loop_level):
self.wire(self.loop_iter.ranges[i], self.current_dma_header[f"range_{i}"])
# Cycle stride
self.cycle_stride_sched_gen = GlbSchedGen(self._params)
self.add_child("cycle_stride_sched_gen",
self.cycle_stride_sched_gen,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
restart=self.st_dma_start_pulse_r,
cycle_count=self.cycle_count,
current_addr=self.cycle_current_addr,
finished=self.loop_done,
valid_output=self.cycle_valid)
self.cycle_stride_addr_gen = GlbAddrGen(self._params)
self.add_child("cycle_stride_addr_gen",
self.cycle_stride_addr_gen,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
restart=self.st_dma_start_pulse_r,
step=self.cycle_valid_muxed,
mux_sel=self.loop_mux_sel,
addr_out=self.cycle_current_addr)
self.wire(self.cycle_stride_addr_gen.start_addr, ext(
self.current_dma_header[f"cycle_start_addr"], self._params.axi_data_width))
for i in range(self._params.loop_level):
self.wire(self.cycle_stride_addr_gen.strides[i],
self.current_dma_header[f"cycle_stride_{i}"])
# Data stride
self.data_stride_addr_gen = GlbAddrGen(self._params)
self.add_child("data_stride_addr_gen",
self.data_stride_addr_gen,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
restart=self.st_dma_start_pulse_r,
step=self.cycle_valid_muxed,
mux_sel=self.loop_mux_sel,
addr_out=self.data_current_addr)
self.wire(self.data_stride_addr_gen.start_addr, ext(
self.current_dma_header[f"start_addr"], self._params.axi_data_width))
for i in range(self._params.loop_level):
self.wire(self.data_stride_addr_gen.strides[i], self.current_dma_header[f"stride_{i}"])
def __init__(self, _params: GlobalBufferParams):
# TODO: configuration wiring to children modules should be a pass
super().__init__("glb_core")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.clk_en = self.input("clk_en", 1)
self.reset = self.reset("reset")
self.glb_tile_id = self.input("glb_tile_id", self._params.tile_sel_addr_width)
self.proc_packet_w2e_wsti = self.input("proc_packet_w2e_wsti", self.header.packet_t)
self.proc_packet_e2w_wsto = self.output("proc_packet_e2w_wsto", self.header.packet_t)
self.proc_packet_e2w_esti = self.input("proc_packet_e2w_esti", self.header.packet_t)
self.proc_packet_w2e_esto = self.output("proc_packet_w2e_esto", self.header.packet_t)
self.strm_packet_w2e_wsti = self.input("strm_packet_w2e_wsti", self.header.packet_t)
self.strm_packet_e2w_wsto = self.output("strm_packet_e2w_wsto", self.header.packet_t)
self.strm_packet_e2w_esti = self.input("strm_packet_e2w_esti", self.header.packet_t)
self.strm_packet_w2e_esto = self.output("strm_packet_w2e_esto", self.header.packet_t)
self.pcfg_packet_w2e_wsti = self.input("pcfg_packet_w2e_wsti", self.header.rd_packet_t)
self.pcfg_packet_e2w_wsto = self.output("pcfg_packet_e2w_wsto", self.header.rd_packet_t)
self.pcfg_packet_e2w_esti = self.input("pcfg_packet_e2w_esti", self.header.rd_packet_t)
self.pcfg_packet_w2e_esto = self.output("pcfg_packet_w2e_esto", self.header.rd_packet_t)
self.strm_data_f2g = self.input("strm_data_f2g", self._params.cgra_data_width,
size=self._params.cgra_per_glb, packed=True)
self.strm_data_valid_f2g = self.input("strm_data_valid_f2g", 1, size=self._params.cgra_per_glb, packed=True)
self.strm_data_g2f = self.output("strm_data_g2f", self._params.cgra_data_width,
size=self._params.cgra_per_glb, packed=True)
self.strm_data_valid_g2f = self.output("strm_data_valid_g2f", 1, size=self._params.cgra_per_glb, packed=True)
# config port
self.sram_cfg_ifc = GlbConfigInterface(addr_width=self._params.glb_addr_width,
data_width=self._params.axi_data_width)
self.if_sram_cfg_est_m = self.interface(self.sram_cfg_ifc.master, "if_sram_cfg_est_m", is_port=True)
self.if_sram_cfg_wst_s = self.interface(self.sram_cfg_ifc.slave, "if_sram_cfg_wst_s", is_port=True)
# configuration registers
self.cfg_data_network_connected_prev = self.input("cfg_data_network_connected_prev", 1)
self.cfg_pcfg_network_connected_prev = self.input("cfg_pcfg_network_connected_prev", 1)
self.cfg_data_network = self.input("cfg_data_network", self.header.cfg_data_network_t)
self.cfg_pcfg_network = self.input("cfg_pcfg_network", self.header.cfg_pcfg_network_t)
# st dma
self.cfg_st_dma_ctrl = self.input("cfg_st_dma_ctrl", self.header.cfg_dma_ctrl_t)
self.cfg_st_dma_header = self.input("cfg_st_dma_header", self.header.cfg_dma_header_t,
size=self._params.queue_depth)
# ld dma
self.cfg_ld_dma_ctrl = self.input("cfg_ld_dma_ctrl", self.header.cfg_dma_ctrl_t)
self.cfg_ld_dma_header = self.input("cfg_ld_dma_header", self.header.cfg_dma_header_t,
size=self._params.queue_depth)
# pcfg dma
self.cfg_pcfg_dma_ctrl = self.input("cfg_pcfg_dma_ctrl", self.header.cfg_pcfg_dma_ctrl_t)
self.cfg_pcfg_dma_header = self.input("cfg_pcfg_dma_header", self.header.cfg_pcfg_dma_header_t)
self.cgra_cfg_pcfg = self.output("cgra_cfg_pcfg", self.header.cgra_cfg_t)
self.ld_dma_start_pulse = self.input("ld_dma_start_pulse", 1)
self.ld_dma_done_pulse = self.output("ld_dma_done_pulse", 1)
self.st_dma_start_pulse = self.input("st_dma_start_pulse", 1)
self.st_dma_done_pulse = self.output("st_dma_done_pulse", 1)
self.pcfg_start_pulse = self.input("pcfg_start_pulse", 1)
self.pcfg_done_pulse = self.output("pcfg_done_pulse", 1)
self.strm_data_g2f_dma2mux = self.var("strm_data_g2f_dma2mux", self._params.cgra_data_width)
self.strm_data_valid_g2f_dma2mux = self.var("strm_data_valid_g2f_dma2mux", 1)
self.strm_data_f2g_mux2dma = self.var("strm_data_f2g_mux2dma", self._params.cgra_data_width)
self.strm_data_valid_f2g_mux2dma = self.var("strm_data_valid_f2g_mux2dma", 1)
self.wr_packet_pr2sw = self.var("wr_packet_pr2sw", self.header.wr_packet_t)
self.wr_packet_sr2sw = self.var("wr_packet_sr2sw", self.header.wr_packet_t)
self.wr_packet_sw2sr = self.var("wr_packet_sw2sr", self.header.wr_packet_t)
self.wr_packet_dma2sw = self.var("wr_packet_dma2sw", self.header.wr_packet_t)
self.wr_packet_sw2bankarr = self.var(
"wr_packet_sw2bankarr", self.header.wr_packet_t, size=self._params.banks_per_tile)
self.rdrq_packet_pr2sw = self.var("rdrq_packet_pr2sw", self.header.rdrq_packet_t)
self.rdrq_packet_sr2sw = self.var("rdrq_packet_sr2sw", self.header.rdrq_packet_t)
self.rdrq_packet_sw2sr = self.var("rdrq_packet_sw2sr", self.header.rdrq_packet_t)
self.rdrq_packet_dma2sw = self.var("rdrq_packet_dma2sw", self.header.rdrq_packet_t)
self.rdrq_packet_pcfgdma2sw = self.var("rdrq_packet_pcfgdma2sw", self.header.rdrq_packet_t)
self.rdrq_packet_pcfgr2sw = self.var("rdrq_packet_pcfgr2sw", self.header.rdrq_packet_t)
self.rdrq_packet_sw2pcfgr = self.var("rdrq_packet_sw2pcfgr", self.header.rdrq_packet_t)
self.rdrq_packet_sw2bankarr = self.var(
"rdrq_packet_sw2bankarr", self.header.rdrq_packet_t, size=self._params.banks_per_tile)
self.rdrs_packet_sw2pr = self.var("rdrs_packet_sw2pr", self.header.rdrs_packet_t)
self.rdrs_packet_sr2sw = self.var("rdrs_packet_sr2sw", self.header.rdrs_packet_t)
self.rdrs_packet_sw2sr = self.var("rdrs_packet_sw2sr", self.header.rdrs_packet_t)
self.rdrs_packet_sw2dma = self.var("rdrs_packet_sw2dma", self.header.rdrs_packet_t)
self.rdrs_packet_pcfgr2sw = self.var("rdrs_packet_pcfgr2sw", self.header.rdrs_packet_t)
self.rdrs_packet_sw2pcfgr = self.var("rdrs_packet_sw2pcfgr", self.header.rdrs_packet_t)
self.rdrs_packet_sw2pcfgdma = self.var("rdrs_packet_sw2pcfgdma", self.header.rdrs_packet_t)
self.rdrs_packet_bankarr2sw = self.var(
"rdrs_packet_bankarr2sw", self.header.rdrs_packet_t, size=self._params.banks_per_tile)
self.packet_sr2sw = self.var("packet_sr2sw", self.header.packet_t)
self.packet_sw2sr = self.var("packet_sw2sr", self.header.packet_t)
self.rd_packet_pcfgr2sw = self.var("rd_packet_pcfgr2sw", self.header.rd_packet_t)
self.rd_packet_sw2pcfgr = self.var("rd_packet_sw2pcfgr", self.header.rd_packet_t)
self.if_sram_cfg_bank2core = []
for i in range(self._params.banks_per_tile):
if_sram_cfg_bank2core = self.interface(GlbConfigInterface(addr_width=self._params.bank_addr_width,
data_width=self._params.axi_data_width),
f"if_sram_cfg_bank2core_{i}")
self.if_sram_cfg_bank2core.append(if_sram_cfg_bank2core)
self.glb_bank_arr = []
for i in range(self._params.banks_per_tile):
glb_bank = GlbBank(self._params)
self.add_child(f"glb_bank_{i}",
glb_bank,
clk=self.clk,
reset=self.reset,
wr_packet=self.wr_packet_sw2bankarr[i],
rdrq_packet=self.rdrq_packet_sw2bankarr[i],
rdrs_packet=self.rdrs_packet_bankarr2sw[i],
if_sram_cfg_s=self.if_sram_cfg_bank2core[i])
self.glb_bank_arr.append(glb_bank)
self.glb_core_sram_cfg_ctrl = GlbCoreSramCfgCtrl(self._params)
self.add_child("glb_core_sram_cfg_ctrl",
self.glb_core_sram_cfg_ctrl,
clk=self.clk,
reset=self.reset,
glb_tile_id=self.glb_tile_id,
if_sram_cfg_est_m=self.if_sram_cfg_est_m,
if_sram_cfg_wst_s=self.if_sram_cfg_wst_s)
for i in range(self._params.banks_per_tile):
self.wire(self.glb_core_sram_cfg_ctrl.if_sram_cfg_core2bank_m[i],
self.if_sram_cfg_bank2core[i])
self.add_child("glb_core_store_dma",
GlbCoreStoreDma(_params=self._params),
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
data_f2g=self.strm_data_f2g_mux2dma,
data_valid_f2g=self.strm_data_valid_f2g_mux2dma,
wr_packet=self.wr_packet_dma2sw,
# TODO: How to make this automatic
cfg_st_dma_num_repeat=self.cfg_st_dma_ctrl['num_repeat'],
cfg_st_dma_ctrl_use_valid=self.cfg_st_dma_ctrl['use_valid'],
cfg_st_dma_ctrl_mode=self.cfg_st_dma_ctrl['mode'],
cfg_data_network_latency=self.cfg_data_network['latency'],
cfg_st_dma_header=self.cfg_st_dma_header,
st_dma_start_pulse=self.st_dma_start_pulse,
st_dma_done_pulse=self.st_dma_done_pulse)
self.add_child("glb_core_load_dma",
GlbCoreLoadDma(_params=self._params),
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
data_g2f=self.strm_data_g2f_dma2mux,
data_valid_g2f=self.strm_data_valid_g2f_dma2mux,
rdrq_packet=self.rdrq_packet_dma2sw,
rdrs_packet=self.rdrs_packet_sw2dma,
# TODO: How to make this automatic
cfg_ld_dma_num_repeat=self.cfg_ld_dma_ctrl['num_repeat'],
cfg_ld_dma_ctrl_use_valid=self.cfg_ld_dma_ctrl['use_valid'],
cfg_ld_dma_ctrl_mode=self.cfg_ld_dma_ctrl['mode'],
cfg_data_network_latency=self.cfg_data_network['latency'],
cfg_ld_dma_header=self.cfg_ld_dma_header,
ld_dma_start_pulse=self.ld_dma_start_pulse,
ld_dma_done_pulse=self.ld_dma_done_pulse)
self.add_child("glb_core_pcfg_dma",
GlbCorePcfgDma(_params=self._params),
clk=self.clk,
reset=self.reset,
cgra_cfg_pcfg=self.cgra_cfg_pcfg,
rdrq_packet=self.rdrq_packet_pcfgdma2sw,
rdrs_packet=self.rdrs_packet_sw2pcfgdma,
# TODO: How to make this automatic
cfg_pcfg_dma_ctrl_mode=self.cfg_pcfg_dma_ctrl['mode'],
cfg_pcfg_network_latency=self.cfg_pcfg_network['latency'],
cfg_pcfg_dma_header=self.cfg_pcfg_dma_header,
pcfg_start_pulse=self.pcfg_start_pulse,
pcfg_done_pulse=self.pcfg_done_pulse)
self.add_child("glb_core_strm_mux",
GlbCoreStrmMux(_params=self._params),
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
data_g2f_dma=self.strm_data_g2f_dma2mux,
data_valid_g2f_dma=self.strm_data_valid_g2f_dma2mux,
data_g2f=self.strm_data_g2f,
data_valid_g2f=self.strm_data_valid_g2f,
data_f2g_dma=self.strm_data_f2g_mux2dma,
data_valid_f2g_dma=self.strm_data_valid_f2g_mux2dma,
data_f2g=self.strm_data_f2g,
data_valid_f2g=self.strm_data_valid_f2g,
cfg_data_network_g2f_mux=self.cfg_ld_dma_ctrl['data_mux'],
cfg_data_network_f2g_mux=self.cfg_st_dma_ctrl['data_mux'])
self.glb_core_switch = GlbCoreSwitch(_params=self._params)
self.add_child("glb_core_switch",
self.glb_core_switch,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
glb_tile_id=self.glb_tile_id,
wr_packet_pr2sw=self.wr_packet_pr2sw,
wr_packet_dma2sw=self.wr_packet_dma2sw,
wr_packet_sw2bankarr=self.wr_packet_sw2bankarr,
rdrq_packet_pr2sw=self.rdrq_packet_pr2sw,
rdrq_packet_dma2sw=self.rdrq_packet_dma2sw,
rdrq_packet_pcfgdma2sw=self.rdrq_packet_pcfgdma2sw,
rdrq_packet_sw2bankarr=self.rdrq_packet_sw2bankarr,
rdrs_packet_sw2pr=self.rdrs_packet_sw2pr,
rdrs_packet_sw2dma=self.rdrs_packet_sw2dma,
rdrs_packet_sw2pcfgdma=self.rdrs_packet_sw2pcfgdma,
rdrs_packet_bankarr2sw=self.rdrs_packet_bankarr2sw,
cfg_st_dma_ctrl_mode=self.cfg_st_dma_ctrl['mode'],
cfg_ld_dma_ctrl_mode=self.cfg_ld_dma_ctrl['mode'],
cfg_pcfg_dma_ctrl_mode=self.cfg_pcfg_dma_ctrl['mode'])
for port in self.header.wr_packet_ports:
self.wire(
self.glb_core_switch.wr_packet_sr2sw[port], self.packet_sr2sw[port])
self.wire(
self.glb_core_switch.wr_packet_sw2sr[port], self.packet_sw2sr[port])
for port in self.header.rdrq_packet_ports:
self.wire(
self.glb_core_switch.rdrq_packet_sr2sw[port], self.packet_sr2sw[port])
self.wire(
self.glb_core_switch.rdrq_packet_sw2sr[port], self.packet_sw2sr[port])
self.wire(
self.glb_core_switch.rdrq_packet_pcfgr2sw[port], self.rd_packet_pcfgr2sw[port])
self.wire(
self.glb_core_switch.rdrq_packet_sw2pcfgr[port], self.rd_packet_sw2pcfgr[port])
for port in self.header.rdrs_packet_ports:
self.wire(
self.glb_core_switch.rdrs_packet_sr2sw[port], self.packet_sr2sw[port])
self.wire(
self.glb_core_switch.rdrs_packet_sw2sr[port], self.packet_sw2sr[port])
self.wire(
self.glb_core_switch.rdrs_packet_pcfgr2sw[port], self.rd_packet_pcfgr2sw[port])
self.wire(
self.glb_core_switch.rdrs_packet_sw2pcfgr[port], self.rd_packet_sw2pcfgr[port])
self.add_child("glb_core_proc_router",
GlbCoreProcRouter(_params=self._params),
clk=self.clk,
reset=self.reset,
glb_tile_id=self.glb_tile_id,
packet_w2e_wsti=self.proc_packet_w2e_wsti,
packet_e2w_wsto=self.proc_packet_e2w_wsto,
packet_e2w_esti=self.proc_packet_e2w_esti,
packet_w2e_esto=self.proc_packet_w2e_esto,
wr_packet_pr2sw=self.wr_packet_pr2sw,
rdrq_packet_pr2sw=self.rdrq_packet_pr2sw,
rdrs_packet_sw2pr=self.rdrs_packet_sw2pr)
self.add_child("glb_core_strm_router",
GlbCoreStrmRouter(_params=self._params),
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
glb_tile_id=self.glb_tile_id,
packet_w2e_wsti=self.strm_packet_w2e_wsti,
packet_e2w_wsto=self.strm_packet_e2w_wsto,
packet_e2w_esti=self.strm_packet_e2w_esti,
packet_w2e_esto=self.strm_packet_w2e_esto,
packet_sr2sw=self.packet_sr2sw,
packet_sw2sr=self.packet_sw2sr,
cfg_tile_connected_prev=self.cfg_data_network_connected_prev,
cfg_tile_connected_next=self.cfg_data_network['tile_connected'])
self.add_child("glb_core_pcfg_router",
GlbCorePcfgRouter(_params=self._params),
clk=self.clk,
reset=self.reset,
glb_tile_id=self.glb_tile_id,
rd_packet_w2e_wsti=self.pcfg_packet_w2e_wsti,
rd_packet_e2w_wsto=self.pcfg_packet_e2w_wsto,
rd_packet_e2w_esti=self.pcfg_packet_e2w_esti,
rd_packet_w2e_esto=self.pcfg_packet_w2e_esto,
rd_packet_sw2pcfgr=self.rd_packet_sw2pcfgr,
rd_packet_pcfgr2sw=self.rd_packet_pcfgr2sw,
cfg_tile_connected_prev=self.cfg_pcfg_network_connected_prev,
cfg_tile_connected_next=self.cfg_pcfg_network['tile_connected'])
def __init__(self, _params: GlobalBufferParams):
super().__init__("global_buffer")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.stall = self.input("stall", self._params.num_glb_tiles)
self.reset = self.reset("reset")
# TODO: Why cgra_stall has same width as num_glb_tiles
self.cgra_stall_in = self.input("cgra_stall_in",
self._params.num_glb_tiles)
self.cgra_stall = self.output(
"cgra_stall",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.proc_wr_en = self.input("proc_wr_en", 1)
self.proc_wr_strb = self.input("proc_wr_strb",
self._params.bank_data_width // 8)
self.proc_wr_addr = self.input("proc_wr_addr",
self._params.glb_addr_width)
self.proc_wr_data = self.input("proc_wr_data",
self._params.bank_data_width)
self.proc_rd_en = self.input("proc_rd_en", 1)
self.proc_rd_addr = self.input("proc_rd_addr",
self._params.glb_addr_width)
self.proc_rd_data = self.output("proc_rd_data",
self._params.bank_data_width)
self.proc_rd_data_valid = self.output("proc_rd_data_valid", 1)
self.if_cfg_wr_en = self.input("if_cfg_wr_en", 1)
self.if_cfg_wr_addr = self.input("if_cfg_wr_addr",
self._params.axi_addr_width)
self.if_cfg_wr_data = self.input("if_cfg_wr_data",
self._params.axi_data_width)
self.if_cfg_rd_en = self.input("if_cfg_rd_en", 1)
self.if_cfg_rd_addr = self.input("if_cfg_rd_addr",
self._params.axi_addr_width)
self.if_cfg_rd_data = self.output("if_cfg_rd_data",
self._params.axi_data_width)
self.if_cfg_rd_data_valid = self.output("if_cfg_rd_data_valid", 1)
self.if_sram_cfg_wr_en = self.input("if_sram_cfg_wr_en", 1)
self.if_sram_cfg_wr_addr = self.input("if_sram_cfg_wr_addr",
self._params.glb_addr_width)
self.if_sram_cfg_wr_data = self.input("if_sram_cfg_wr_data",
self._params.axi_data_width)
self.if_sram_cfg_rd_en = self.input("if_sram_cfg_rd_en", 1)
self.if_sram_cfg_rd_addr = self.input("if_sram_cfg_rd_addr",
self._params.glb_addr_width)
self.if_sram_cfg_rd_data = self.output("if_sram_cfg_rd_data",
self._params.axi_data_width)
self.if_sram_cfg_rd_data_valid = self.output(
"if_sram_cfg_rd_data_valid", 1)
self.cgra_cfg_jtag_gc2glb_wr_en = self.input(
"cgra_cfg_jtag_gc2glb_wr_en", 1)
self.cgra_cfg_jtag_gc2glb_rd_en = self.input(
"cgra_cfg_jtag_gc2glb_rd_en", 1)
self.cgra_cfg_jtag_gc2glb_addr = self.input(
"cgra_cfg_jtag_gc2glb_addr", self._params.cgra_cfg_addr_width)
self.cgra_cfg_jtag_gc2glb_data = self.input(
"cgra_cfg_jtag_gc2glb_data", self._params.cgra_cfg_data_width)
self.stream_data_f2g = self.input(
"stream_data_f2g",
self._params.cgra_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.stream_data_valid_f2g = self.input(
"stream_data_valid_f2g",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.stream_data_g2f = self.output(
"stream_data_g2f",
self._params.cgra_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.stream_data_valid_g2f = self.output(
"stream_data_valid_g2f",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.cgra_cfg_g2f_cfg_wr_en = self.output(
"cgra_cfg_g2f_cfg_wr_en",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.cgra_cfg_g2f_cfg_rd_en = self.output(
"cgra_cfg_g2f_cfg_rd_en",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.cgra_cfg_g2f_cfg_addr = self.output(
"cgra_cfg_g2f_cfg_addr",
self._params.cgra_cfg_addr_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.cgra_cfg_g2f_cfg_data = self.output(
"cgra_cfg_g2f_cfg_data",
self._params.cgra_cfg_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.strm_g2f_start_pulse = self.input("strm_g2f_start_pulse",
self._params.num_glb_tiles)
self.strm_f2g_start_pulse = self.input("strm_f2g_start_pulse",
self._params.num_glb_tiles)
self.pcfg_start_pulse = self.input("pcfg_start_pulse",
self._params.num_glb_tiles)
self.strm_f2g_interrupt_pulse = self.output("strm_f2g_interrupt_pulse",
self._params.num_glb_tiles)
self.strm_g2f_interrupt_pulse = self.output("strm_g2f_interrupt_pulse",
self._params.num_glb_tiles)
self.pcfg_g2f_interrupt_pulse = self.output("pcfg_g2f_interrupt_pulse",
self._params.num_glb_tiles)
# local variables
self.cgra_cfg_jtag_gc2glb_wr_en_d = self.var(
"cgra_cfg_jtag_gc2glb_wr_en_d", 1)
self.cgra_cfg_jtag_gc2glb_rd_en_d = self.var(
"cgra_cfg_jtag_gc2glb_rd_en_d", 1)
self.cgra_cfg_jtag_gc2glb_addr_d = self.var(
"cgra_cfg_jtag_gc2glb_addr_d", self._params.cgra_cfg_addr_width)
self.cgra_cfg_jtag_gc2glb_data_d = self.var(
"cgra_cfg_jtag_gc2glb_data_d", self._params.cgra_cfg_data_width)
self.proc_packet_d = self.var("proc_packet_d", self.header.packet_t)
self.proc_packet_e2w_esti = self.var("proc_packet_e2w_esti",
self.header.packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.proc_packet_w2e_wsti = self.var("proc_packet_w2e_wsti",
self.header.packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.proc_packet_e2w_wsto = self.var("proc_packet_e2w_wsto",
self.header.packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.proc_packet_w2e_esto = self.var("proc_packet_w2e_esto",
self.header.packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.strm_packet_e2w_esti = self.var("strm_packet_e2w_esti",
self.header.packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.strm_packet_w2e_wsti = self.var("strm_packet_w2e_wsti",
self.header.packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.strm_packet_e2w_wsto = self.var("strm_packet_e2w_wsto",
self.header.packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.strm_packet_w2e_esto = self.var("strm_packet_w2e_esto",
self.header.packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.pcfg_packet_e2w_esti = self.var("pcfg_packet_e2w_esti",
self.header.rd_packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.pcfg_packet_w2e_wsti = self.var("pcfg_packet_w2e_wsti",
self.header.rd_packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.pcfg_packet_e2w_wsto = self.var("pcfg_packet_e2w_wsto",
self.header.rd_packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.pcfg_packet_w2e_esto = self.var("pcfg_packet_w2e_esto",
self.header.rd_packet_t,
size=self._params.num_glb_tiles,
packed=True)
self.cfg_tile_connected = self.var("cfg_tile_connected",
self._params.num_glb_tiles + 1)
self.cfg_pcfg_tile_connected = self.var("cfg_pcfg_tile_connected",
self._params.num_glb_tiles + 1)
self.wire(self.cfg_tile_connected[0], 0)
self.wire(self.cfg_pcfg_tile_connected[0], 0)
self.cgra_cfg_jtag_wsti_wr_en = self.var(
"cgra_cfg_jtag_wsti_wr_en",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_wsti_rd_en = self.var(
"cgra_cfg_jtag_wsti_rd_en",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_wsti_addr = self.var(
"cgra_cfg_jtag_wsti_addr",
self._params.cgra_cfg_addr_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_wsti_data = self.var(
"cgra_cfg_jtag_wsti_data",
self._params.cgra_cfg_data_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_esto_wr_en = self.var(
"cgra_cfg_jtag_esto_wr_en",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_esto_rd_en = self.var(
"cgra_cfg_jtag_esto_rd_en",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_esto_addr = self.var(
"cgra_cfg_jtag_esto_addr",
self._params.cgra_cfg_addr_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_esto_data = self.var(
"cgra_cfg_jtag_esto_data",
self._params.cgra_cfg_data_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_wsti_rd_en_bypass = self.var(
"cgra_cfg_jtag_wsti_rd_en_bypass",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_wsti_addr_bypass = self.var(
"cgra_cfg_jtag_wsti_addr_bypass",
self._params.cgra_cfg_addr_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_esto_rd_en_bypass = self.var(
"cgra_cfg_jtag_esto_rd_en_bypass",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_jtag_esto_addr_bypass = self.var(
"cgra_cfg_jtag_esto_addr_bypass",
self._params.cgra_cfg_addr_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_pcfg_wsti_wr_en = self.var(
"cgra_cfg_pcfg_wsti_wr_en",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_pcfg_wsti_rd_en = self.var(
"cgra_cfg_pcfg_wsti_rd_en",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_pcfg_wsti_addr = self.var(
"cgra_cfg_pcfg_wsti_addr",
self._params.cgra_cfg_addr_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_pcfg_wsti_data = self.var(
"cgra_cfg_pcfg_wsti_data",
self._params.cgra_cfg_data_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_pcfg_esto_wr_en = self.var(
"cgra_cfg_pcfg_esto_wr_en",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_pcfg_esto_rd_en = self.var(
"cgra_cfg_pcfg_esto_rd_en",
1,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_pcfg_esto_addr = self.var(
"cgra_cfg_pcfg_esto_addr",
self._params.cgra_cfg_addr_width,
size=self._params.num_glb_tiles,
packed=True)
self.cgra_cfg_pcfg_esto_data = self.var(
"cgra_cfg_pcfg_esto_data",
self._params.cgra_cfg_data_width,
size=self._params.num_glb_tiles,
packed=True)
self.stall_w = self.var("stall_w", self._params.num_glb_tiles)
self.stall_d = self.var("stall_d", self._params.num_glb_tiles)
self.wire(self.stall_w, self.stall)
self.cgra_stall_in_w = self.var("cgra_stall_in_w",
self._params.num_glb_tiles)
self.cgra_stall_in_d = self.var("cgra_stall_in_d",
self._params.num_glb_tiles)
self.wire(self.cgra_stall_in_w, self.cgra_stall_in)
for i in range(self._params.num_glb_tiles):
self.wire(
self.cgra_stall[i],
concat(*[self.cgra_stall_in_d[i]] * self._params.cgra_per_glb))
self.strm_g2f_start_pulse_w = self.var("strm_g2f_start_pulse_w",
self._params.num_glb_tiles)
self.strm_g2f_start_pulse_d = self.var("strm_g2f_start_pulse_d",
self._params.num_glb_tiles)
self.wire(self.strm_g2f_start_pulse, self.strm_g2f_start_pulse_w)
self.strm_f2g_start_pulse_w = self.var("strm_f2g_start_pulse_w",
self._params.num_glb_tiles)
self.strm_f2g_start_pulse_d = self.var("strm_f2g_start_pulse_d",
self._params.num_glb_tiles)
self.wire(self.strm_f2g_start_pulse, self.strm_f2g_start_pulse_w)
self.pcfg_start_pulse_w = self.var("pcfg_start_pulse_w",
self._params.num_glb_tiles)
self.pcfg_start_pulse_d = self.var("pcfg_start_pulse_d",
self._params.num_glb_tiles)
self.wire(self.pcfg_start_pulse, self.pcfg_start_pulse_w)
self.strm_f2g_interrupt_pulse_w = self.var(
"strm_f2g_interrupt_pulse_w", self._params.num_glb_tiles)
self.strm_f2g_interrupt_pulse_d = self.var(
"strm_f2g_interrupt_pulse_d", self._params.num_glb_tiles)
self.wire(self.strm_f2g_interrupt_pulse_d,
self.strm_f2g_interrupt_pulse)
self.strm_g2f_interrupt_pulse_w = self.var(
"strm_g2f_interrupt_pulse_w", self._params.num_glb_tiles)
self.strm_g2f_interrupt_pulse_d = self.var(
"strm_g2f_interrupt_pulse_d", self._params.num_glb_tiles)
self.wire(self.strm_g2f_interrupt_pulse_d,
self.strm_g2f_interrupt_pulse)
self.pcfg_g2f_interrupt_pulse_w = self.var(
"pcfg_g2f_interrupt_pulse_w", self._params.num_glb_tiles)
self.pcfg_g2f_interrupt_pulse_d = self.var(
"pcfg_g2f_interrupt_pulse_d", self._params.num_glb_tiles)
self.wire(self.pcfg_g2f_interrupt_pulse_d,
self.pcfg_g2f_interrupt_pulse)
self.cgra_cfg_g2f_cfg_wr_en_w = self.var(
"cgra_cfg_g2f_cfg_wr_en_w",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.cgra_cfg_g2f_cfg_wr_en_d = self.var(
"cgra_cfg_g2f_cfg_wr_en_d",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.wire(self.cgra_cfg_g2f_cfg_wr_en_d, self.cgra_cfg_g2f_cfg_wr_en)
self.cgra_cfg_g2f_cfg_rd_en_w = self.var(
"cgra_cfg_g2f_cfg_rd_en_w",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.cgra_cfg_g2f_cfg_rd_en_d = self.var(
"cgra_cfg_g2f_cfg_rd_en_d",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.wire(self.cgra_cfg_g2f_cfg_rd_en_d, self.cgra_cfg_g2f_cfg_rd_en)
self.cgra_cfg_g2f_cfg_addr_w = self.var(
"cgra_cfg_g2f_cfg_addr_w",
self._params.cgra_cfg_addr_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.cgra_cfg_g2f_cfg_addr_d = self.var(
"cgra_cfg_g2f_cfg_addr_d",
self._params.cgra_cfg_addr_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.wire(self.cgra_cfg_g2f_cfg_addr_d, self.cgra_cfg_g2f_cfg_addr)
self.cgra_cfg_g2f_cfg_data_w = self.var(
"cgra_cfg_g2f_cfg_data_w",
self._params.cgra_cfg_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.cgra_cfg_g2f_cfg_data_d = self.var(
"cgra_cfg_g2f_cfg_data_d",
self._params.cgra_cfg_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.wire(self.cgra_cfg_g2f_cfg_data_d, self.cgra_cfg_g2f_cfg_data)
self.stream_data_f2g_w = self.var(
"stream_data_f2g_w",
self._params.cgra_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.stream_data_f2g_d = self.var(
"stream_data_f2g_d",
self._params.cgra_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.wire(self.stream_data_f2g, self.stream_data_f2g_w)
self.stream_data_valid_f2g_w = self.var(
"stream_data_valid_f2g_w",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.stream_data_valid_f2g_d = self.var(
"stream_data_valid_f2g_d",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.wire(self.stream_data_valid_f2g, self.stream_data_valid_f2g_w)
self.stream_data_g2f_w = self.var(
"stream_data_g2f_w",
self._params.cgra_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.stream_data_g2f_d = self.var(
"stream_data_g2f_d",
self._params.cgra_data_width,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.wire(self.stream_data_g2f_d, self.stream_data_g2f)
self.stream_data_valid_g2f_w = self.var(
"stream_data_valid_g2f_w",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.stream_data_valid_g2f_d = self.var(
"stream_data_valid_g2f_d",
1,
size=[self._params.num_glb_tiles, self._params.cgra_per_glb],
packed=True)
self.wire(self.stream_data_valid_g2f_d, self.stream_data_valid_g2f)
# interface
if_cfg_tile2tile = GlbConfigInterface(
addr_width=self._params.axi_addr_width,
data_width=self._params.axi_data_width)
if_sram_cfg_tile2tile = GlbConfigInterface(
addr_width=self._params.glb_addr_width,
data_width=self._params.axi_data_width)
self.if_cfg_list = []
self.if_sram_cfg_list = []
for i in range(self._params.num_glb_tiles + 1):
self.if_cfg_list.append(
self.interface(if_cfg_tile2tile, f"if_cfg_tile2tile_{i}"))
self.if_sram_cfg_list.append(
self.interface(if_sram_cfg_tile2tile,
f"if_sram_cfg_tile2tile_{i}"))
self.glb_tile = []
for i in range(self._params.num_glb_tiles):
self.glb_tile.append(GlbTile(_params=self._params))
self.wire(self.if_cfg_list[-1].rd_data, 0)
self.wire(self.if_cfg_list[-1].rd_data_valid, 0)
self.wire(self.if_sram_cfg_list[-1].rd_data, 0)
self.wire(self.if_sram_cfg_list[-1].rd_data_valid, 0)
self.add_glb_tile()
self.add_always(self.left_edge_proc_ff)
self.add_always(self.left_edge_cfg_ff)
self.add_always(self.left_edge_sram_cfg_ff)
self.add_always(self.left_edge_cgra_cfg_ff)
self.tile2tile_e2w_wiring()
self.tile2tile_w2e_wiring()
self.add_always(self.tile2tile_w2e_cfg_wiring)
self.add_always(self.interrupt_pipeline)
self.add_always(self.start_pulse_pipeline)
self.add_always(self.stall_pipeline)
self.add_always(self.stream_data_pipeline)
self.add_always(self.cgra_cfg_pcfg_pipeline)
def __init__(self, _params: GlobalBufferParams):
super().__init__("glb_core_switch")
self._params = _params
self.header = GlbHeader(self._params)
self.clk = self.clock("clk")
self.clk_en = self.input("clk_en", 1)
self.reset = self.reset("reset")
self.glb_tile_id = self.input(
"glb_tile_id", self._params.tile_sel_addr_width)
# wr packet
self.wr_packet_pr2sw = self.input(
"wr_packet_pr2sw", self.header.wr_packet_t)
self.wr_packet_sr2sw = self.input(
"wr_packet_sr2sw", self.header.wr_packet_t)
self.wr_packet_sw2sr = self.output(
"wr_packet_sw2sr", self.header.wr_packet_t)
self.wr_packet_dma2sw = self.input(
"wr_packet_dma2sw", self.header.wr_packet_t)
self.wr_packet_sw2bankarr = self.output(
"wr_packet_sw2bankarr", self.header.wr_packet_t, size=self._params.banks_per_tile)
# rdrq packet
self.rdrq_packet_pr2sw = self.input(
"rdrq_packet_pr2sw", self.header.rdrq_packet_t)
self.rdrq_packet_sr2sw = self.input(
"rdrq_packet_sr2sw", self.header.rdrq_packet_t)
self.rdrq_packet_sw2sr = self.output(
"rdrq_packet_sw2sr", self.header.rdrq_packet_t)
self.rdrq_packet_dma2sw = self.input(
"rdrq_packet_dma2sw", self.header.rdrq_packet_t)
self.rdrq_packet_pcfgr2sw = self.input(
"rdrq_packet_pcfgr2sw", self.header.rdrq_packet_t)
self.rdrq_packet_sw2pcfgr = self.output(
"rdrq_packet_sw2pcfgr", self.header.rdrq_packet_t)
self.rdrq_packet_pcfgdma2sw = self.input(
"rdrq_packet_pcfgdma2sw", self.header.rdrq_packet_t)
self.rdrq_packet_sw2bankarr = self.output(
"rdrq_packet_sw2bankarr", self.header.rdrq_packet_t, size=self._params.banks_per_tile)
# rdrq packet
self.rdrs_packet_sw2pr = self.output(
"rdrs_packet_sw2pr", self.header.rdrs_packet_t)
self.rdrs_packet_sr2sw = self.input(
"rdrs_packet_sr2sw", self.header.rdrs_packet_t)
self.rdrs_packet_sw2sr = self.output(
"rdrs_packet_sw2sr", self.header.rdrs_packet_t)
self.rdrs_packet_sw2dma = self.output(
"rdrs_packet_sw2dma", self.header.rdrs_packet_t)
self.rdrs_packet_pcfgr2sw = self.input(
"rdrs_packet_pcfgr2sw", self.header.rdrs_packet_t)
self.rdrs_packet_sw2pcfgr = self.output(
"rdrs_packet_sw2pcfgr", self.header.rdrs_packet_t)
self.rdrs_packet_sw2pcfgdma = self.output(
"rdrs_packet_sw2pcfgdma", self.header.rdrs_packet_t)
self.rdrs_packet_bankarr2sw = self.input(
"rdrs_packet_bankarr2sw", self.header.rdrs_packet_t, size=self._params.banks_per_tile)
# configuration
self.cfg_st_dma_ctrl_mode = self.input("cfg_st_dma_ctrl_mode", 2)
self.cfg_ld_dma_ctrl_mode = self.input("cfg_ld_dma_ctrl_mode", 2)
self.cfg_pcfg_dma_ctrl_mode = self.input("cfg_pcfg_dma_ctrl_mode", 1)
# local variables
assert self._params.glb_switch_pipeline_depth == 1 # switch pipeline depth is fixed to 1
self.wr_packet_sr2sw_d = self.var(
"wr_packet_sr2sw_d", self.header.wr_packet_t)
self.wr_packet_pr2sw_d = self.var(
"wr_packet_pr2sw_d", self.header.wr_packet_t)
self.wr_packet_dma2sw_d = self.var(
"wr_packet_dma2sw_d", self.header.wr_packet_t)
self.wr_packet_sw2bank_muxed = self.var(
"wr_packet_sw2bank_muxed", self.header.wr_packet_t)
self.wr_packet_sw2bank_filtered = self.var(
"wr_packet_sw2bank_filtered", self.header.wr_packet_t)
self.rdrq_packet_pr2sw_d = self.var(
"rdrq_packet_pr2sw_d", self.header.rdrq_packet_t)
self.rdrq_packet_sr2sw_d = self.var(
"rdrq_packet_sr2sw_d", self.header.rdrq_packet_t)
self.rdrq_packet_dma2sw_d = self.var(
"rdrq_packet_dma2sw_d", self.header.rdrq_packet_t)
self.rdrq_packet_pcfgr2sw_d = self.var(
"rdrq_packet_pcfgr2sw_d", self.header.rdrq_packet_t)
self.rdrq_packet_pcfgdma2sw_d = self.var(
"rdrq_packet_pcfgdma2sw_d", self.header.rdrq_packet_t)
self.rdrq_packet_sw2bank_muxed = self.var(
"rdrq_packet_sw2bank_muxed", self.header.rdrq_packet_t)
self.rdrs_packet_pcfgr2sw_d = self.var(
"rdrs_packet_pcfgr2sw_d", self.header.rdrs_packet_t)
self.rdrs_packet_sr2sw_d = self.var(
"rdrs_packet_sr2sw_d", self.header.rdrs_packet_t)
self.rdrs_packet_bankarr2sw_sr_d = self.var(
"rdrs_packet_bankarr2sw_sr_d ", self.header.rdrs_packet_t, size=self._params.banks_per_tile)
self.rdrs_packet_bankarr2sw_pr_d = self.var(
"rdrs_packet_bankarr2sw_pr_d ", self.header.rdrs_packet_t, size=self._params.banks_per_tile)
self.rdrs_packet_bankarr2sw_pcfgr_d = self.var(
"rdrs_packet_bankarr2sw_pcfgr_d ", self.header.rdrs_packet_t, size=self._params.banks_per_tile)
# packet src enum
self.packet_src_e = self.enum("packet_src_e", {
"none": 0, "proc": 1, "strm_dma": 2, "strm_rtr": 3, "pcfg_dma": 4, "pcfg_rtr": 5})
# TODO: Kratos doesn't support array of enum instances yet
self.rdrq_sel = self.var("rdrq_sel", self.packet_src_e)
self.rdrq_sel_d = []
self.rdrq_sel_d_nostall = []
for i in range(self._params.glb_bank_memory_pipeline_depth
+ self._params.sram_gen_pipeline_depth
+ self._params.sram_gen_output_pipeline_depth
+ self._params.glb_switch_pipeline_depth
+ 1):
self.rdrq_sel_d.append(
self.var(f"rdrq_sel_d{i+1}", self.packet_src_e))
self.rdrq_sel_d_nostall.append(
self.var(f"rdrq_sel_d{i+1}_nostall", self.packet_src_e))
self.rdrq_bank_sel = self.var(
"rdrq_bank_sel", self._params.bank_sel_addr_width)
self.rdrq_bank_sel_d = []
self.rdrq_bank_sel_d_nostall = []
for i in range(self._params.glb_bank_memory_pipeline_depth
+ self._params.sram_gen_pipeline_depth
+ self._params.sram_gen_output_pipeline_depth
+ self._params.glb_switch_pipeline_depth
+ 1):
self.rdrq_bank_sel_d.append(
self.var(f"rdrq_bank_sel_d{i+1}", self._params.bank_sel_addr_width))
self.rdrq_bank_sel_d_nostall.append(
self.var(f"rdrq_bank_sel_d{i+1}_nostall", self._params.bank_sel_addr_width))
self.wr_bank_sel = self.var(
"wr_bank_sel", self._params.bank_sel_addr_width)
# localparam
self.packet_addr_tile_sel_msb = _params.bank_addr_width + \
_params.bank_sel_addr_width + _params.tile_sel_addr_width - 1
self.packet_addr_tile_sel_lsb = _params.bank_addr_width + _params.bank_sel_addr_width
self.packet_addr_bank_sel_msb = _params.bank_addr_width + \
_params.bank_sel_addr_width - 1
self.packet_addr_bank_sel_lsb = _params.bank_addr_width
# Add always statements
# wr packet
self.add_always(self.wr_proc_pipeline)
self.add_always(self.wr_data_pipeline)
self.add_always(self.wr_sw2bank_logic)
self.add_always(self.wr_sw2bank_filtered_logic)
self.add_always(self.wr_sw2bankarr_logic)
self.add_always(self.wr_sw2sr_logic)
# rdrq packet
self.add_always(self.rdrq_proc_pcfg_pipeline)
self.add_always(self.rdrq_data_pipeline)
self.add_always(self.rdrq_sel_logic)
self.add_always(self.rdrq_switch_logic)
self.add_always(self.rdrq_sw2bank_logic)
self.add_always(self.rdrq_sw2sr_logic)
self.add_always(self.rdrq_sw2pcfgr_logic)
# rdrq_sel pipeline
for in_, out_ in zip([self.rdrq_sel] + self.rdrq_sel_d[:-1], self.rdrq_sel_d):
self.add_always(self.rdrq_pipeline, in_=in_, out_=out_,
rst=self.packet_src_e.none)
for in_, out_ in zip([self.rdrq_sel] + self.rdrq_sel_d_nostall[:-1], self.rdrq_sel_d_nostall):
self.add_always(self.rdrq_pipeline_nostall, in_=in_,
out_=out_, rst=self.packet_src_e.none)
# rdrq_bank_sel pipeline
for in_, out_ in zip([self.rdrq_bank_sel] + self.rdrq_bank_sel_d[:-1], self.rdrq_bank_sel_d):
self.add_always(self.rdrq_pipeline, in_=in_, out_=out_, rst=0)
for in_, out_ in zip([self.rdrq_bank_sel] + self.rdrq_bank_sel_d_nostall[:-1], self.rdrq_bank_sel_d_nostall):
self.add_always(self.rdrq_pipeline_nostall,
in_=in_, out_=out_, rst=0)
# rdrs packet
self.add_always(self.rdrs_proc_pcfg_pipeline)
self.add_always(self.rdrs_data_pipeline)
self.add_always(self.rdrs_sr2sw_pipieline)
self.add_always(self.rdrs_sw2dma_logic)
self.add_always(self.rdrs_sw2sr_logic)
self.add_always(self.rdrs_sw2pr_logic)
self.add_always(self.rdrs_pcfgr2sw_pipeline)
self.add_always(self.rdrs_sw2pcfgdma_logic)
self.add_always(self.rdrs_sw2pcfgr_logic)