#! /usr/bin/python if __name__ == '__main__': import hacking hacking.reexec('test_shifter.py') import sys from myhdl import (Signal, ResetSignal, TristateSignal, intbv, always_seq, always_comb, instance) from common.system import System from common.clk import Clk from common.rst import rstgen from common.timebase import nsec from common.util import rename_interface from wb import WbBus, WbMux from regfile import RegFile, Port, Field, RoField, RwField from test_wb import wb_write, wb_read from shifter import Shifter, ShifterBus def gen(system, wb_bus, shifter_bus): # Make signals visible in simulation RST_I = wb_bus.RST_I CLK_I = wb_bus.CLK_I CYC_I = wb_bus.CYC_I STB_I = wb_bus.STB_I WE_I = wb_bus.WE_I ACK_O = wb_bus.ACK_O ADR_I = wb_bus.ADR_I DAT_I = wb_bus.DAT_I
#! /usr/bin/python if __name__ == '__main__': import hacking hacking.reexec('test_frontpanel.py') import sys from myhdl import (Signal, ResetSignal, intbv, always, always_comb, instance, delay, toVerilog, Simulation, traceSignals) from common.timebase import nsec from common.util import rename_interface from common.test_system import create_system from simple.mux import Mux from simple.test_bus import sb_write, sb_read from frontpanel import FrontPanel def fake_panel(fp_rst, fp_clk, fp_dout, nr_keys): print "fake_panel", type(fp_rst), type(fp_clk), type(fp_dout), type(nr_keys) insts = [] keys = Signal(intbv(0)[nr_keys:]) n = Signal(intbv(0, 0, nr_keys)) @instance def src():
#! /usr/bin/python if __name__ == '__main__': import hacking hacking.reexec('test_hybrid_counter.py') from myhdl import Signal, intbv, always_comb, always_seq from common.gray import gray_decoder, gray_counter from wb import WbSlave class HybridCounter(WbSlave): """A hybrid asynchronous/synchronous counter which can count higher frequencies than sysclk on a number of pins. An asynchronous gray counter which counts the number of positive edges on a set of pins. Each counter is split into an asynchronous part that can run faster than sysclk and a synchronous part that is updated periodically. The purpose of this counter is to save on the number of ripple carry resources used in an FPGA and to let the asynchronous counters run faster than they could have done otherwise. It's only possible to fit about 80 asynchronous 32 bit counters into a Xilinx XC6SLX9 FPGA before the it runs out of space. With the hybrid approach where only the lower 12 bits are updated asynchronously should be able to fit two or three times as many counters into the same FPGA. An asynchronous gray counter increments the lower async_width of the counter on every positive edge of the pin.
#! /usr/bin/python if __name__ == '__main__': import hacking hacking.reexec('test_hybrid_counter.py') from myhdl import Signal, ConcatSignal, intbv, instance, delay, SignalType from rhea.system import Clock from common.timebase import timescale, nsec, usec, msec, sec from common.clk import Clk from common.rst import rstgen from wb import WbSlaveInterface from hybrid_counter import HybridCounter def test(bus): freqs = [100E6, 133E6, 233E6] pin_array = [] pin_insts = [] for freq in freqs: pin = Clk(freq, False) pin_inst = pin.gen() pin_array.append(pin) pin_insts.append(pin_inst) pins = ConcatSignal(*pin_array) clk = bus.CLK_I rst = bus.RST_I
#! /usr/bin/python if __name__ == '__main__': import hacking hacking.reexec('test_ddr.py') from myhdl import Signal, intbv, always, always_seq, always_comb from common.util import mask, lsh from spartan6 import iobuf_delay_ddr2_fixed class DdrBus(object): def __init__(self, ba_width, a_width, d_width): self.ba_width = ba_width self.a_width = a_width self.d_width = d_width self.CS_B = Signal(True) self.RAS_B = Signal(True) self.CAS_B = Signal(True) self.WE_B = Signal(True) self.BA = Signal(intbv(~0)[ba_width:]) self.A = Signal(intbv(~0)[a_width:]) self.DQS0_O = Signal(intbv(0)[d_width:]) self.DQS0_I = Signal(intbv(0)[d_width:]) self.DQS0_OE = Signal(False) self.DM0_I = Signal(intbv(0)[d_width:]) self.DM0_O = Signal(intbv(0)[d_width:]) self.DM0_OE = Signal(intbv(0)[d_width:])
#! /usr/bin/python if __name__ == '__main__': import hacking hacking.reexec('test_ddr.py') from myhdl import Signal, intbv, always, always_seq, always_comb from common.util import mask, lsh from spartan6 import iobuf_delay_ddr2_fixed class DdrBus(object): def __init__(self, ba_width, a_width, d_width): self.ba_width = ba_width self.a_width = a_width self.d_width = d_width self.CS_B = Signal(True) self.RAS_B = Signal(True) self.CAS_B = Signal(True) self.WE_B = Signal(True) self.BA = Signal(intbv(~0)[ba_width:]) self.A = Signal(intbv(~0)[a_width:]) self.DQS0_O = Signal(intbv(0)[d_width:]) self.DQS0_I = Signal(intbv(0)[d_width:]) self.DQS0_OE = Signal(False) self.DM0_I = Signal(intbv(0)[d_width:]) self.DM0_O = Signal(intbv(0)[d_width:])
#! /usr/bin/python if __name__ == '__main__': import hacking hacking.reexec('image.py') from pprint import pprint from myhdl import (Signal, ResetSignal, TristateSignal, ConcatSignal, intbv, always_comb, always_seq) from rhea.cores.misc import syncro from spartan6 import (startup_spartan6, bufg, ibufds, ibufgds, ibufgds_diff_out, ibufds_vec, iddr2) from common.system import System from common.util import tristate from simple.bus import Bus as SimpleBus from simple.mux import Mux as SimpleMux from simple.algo import Algo from simple.fifo_ram import FifoRam from simple.reg import Reg as SimpleReg from simple.reg import Port as SimplePort from simple.reg import Field as SimpleField from simple.reg import RwField as SimpleRwField from simple.reg import RoField as SimpleRoField from simple.reg import DummyField as SimpleDummyField from fifo.sync import SyncFifo
#! /usr/bin/python if __name__ == '__main__': import hacking hacking.reexec('test_frontpanel.py') import sys from myhdl import (Signal, ResetSignal, intbv, always, always_comb, instance, delay, toVerilog, Simulation, traceSignals) from common.timebase import nsec from common.util import rename_interface from common.test_system import create_system from simple.mux import Mux from simple.test_bus import sb_write, sb_read from frontpanel import FrontPanel def fake_panel(fp_rst, fp_clk, fp_dout, nr_keys): print "fake_panel", type(fp_rst), type(fp_clk), type(fp_dout), type( nr_keys) insts = [] keys = Signal(intbv(0)[nr_keys:]) n = Signal(intbv(0, 0, nr_keys)) @instance