def as_hdl_HdlPortItem(self, o: HdlPortItem):
var = HdlIdDef()
var.direction = HWT_TO_HDLCONVEROTR_DIRECTION[o.direction]
s = o.getInternSig()
var.name = s.name
var.origin = o
var.type = o._dtype
return self.as_hdl_HdlModuleDef_variable(var, (), None, None, None, None)
def _copyParamsAndInterfaces(self):
# note that the parameters are not added to HdlModuleDef (VHDL entity, Verilog module header)
# as it was already build
for p in self._possible_variants[0]._params:
myP = Param(p.get_value())
self._registerParameter(p._name, myP)
myP.set_value(p.get_value())
ns = self._store_manager.name_scope
for p in sorted(self._params, key=lambda x: x._name):
hdl_val = p.get_hdl_value()
v = HdlIdDef()
v.origin = p
v.name = p.hdl_name = ns.checked_name(p._name, p)
v.type = hdl_val._dtype
v.value = hdl_val
self._ctx.ent.params.append(v)
for intf in self.possible_variants[0]._interfaces:
# clone interface
myIntf = copy(intf)
myIntf._dtype = copy(myIntf._dtype)
# sub-interfaces are not instantiated yet
# myIntf._direction = intf._direction
myIntf._direction = INTF_DIRECTION.opposite(intf._direction)
self._registerInterface(intf._name, myIntf)
object.__setattr__(self, intf._name, myIntf)
ei = self._ctx.interfaces
for i in self._interfaces:
self._loadInterface(i, True)
assert i._isExtern
i._signalsForInterface(self._ctx,
ei,
self._store_manager.name_scope,
reverse_dir=True)