def as_hdl_PortConnection(self, o: HdlPortItem): assert isinstance(o, HdlPortItem), o intern, outer = o.getInternSig(), o.getOuterSig() assert not intern.hidden, intern assert not outer.hidden, outer intern_hdl = HdlValueId(intern.name, obj=intern) outer_hdl = HdlValueId(outer.name, obj=outer) pm = hdl_map_asoc(intern_hdl, outer_hdl) return pm
def as_hdl_PortConnection(self, o: HdlPortItem): assert isinstance(o, HdlPortItem), o if o.dst._dtype != o.src._dtype: raise SerializerException( f"Port map {o.name:s} is not valid (types does not match) ({o.src._dtype}, {o.dst._dtype}) " f"{o.src} => {o.dst}") intern, outer = o.getInternSig(), o.getOuterSig() intern_hdl = self.as_hdl_Value(intern) intern_hdl.obj = o outer_hdl = self.as_hdl_Value(outer) pm = hdl_map_asoc(intern_hdl, outer_hdl) return pm
def as_hdl_HdlCompInst(self, o: HdlCompInst) -> HdlCompInst: new_o = copy(o) param_map = [] for p in o.param_map: assert isinstance(p, HdlIdDef), p pm = hdl_map_asoc(HdlValueId(p.name, obj=p), self.as_hdl(p.value)) param_map.append(pm) new_o.param_map = param_map port_map = [] for pi in o.port_map: pm = self.as_hdl_PortConnection(pi) port_map.append(pm) new_o.port_map = port_map return new_o
def as_hdl_PortConnection(self, o: HdlPortItem): assert isinstance(o, HdlPortItem), o if o.dst._dtype != o.src._dtype: raise SerializerException( "Port map %s is not valid (types does not match) (%r, %r) " "%s => %s" % (o.name, o.src._dtype, o.dst._dtype, o.src, o.dst,) ) intern, outer = o.getInternSig(), o.getOuterSig() intern_hdl = self.as_hdl_Value(intern) intern_hdl.obj = o outer_hdl = self.as_hdl_Value(outer) pm = hdl_map_asoc(intern_hdl, outer_hdl) return pm
def add_kw(name, val): kw = hdl_map_asoc(HdlValueId(name), HdlValueInt(val, None, None)) args.append(kw)