def _getSourceByPath(self, path):
"""
Get the source object, flags and any additional info to be displayed
"""
source = None
remarks = []
try:
source = self._config.getSourceByPath(path)
except KeyError:
pass
# If the source file was not found on the configuration file, add this
# as a remark.
# Also, create a source parser object with some library so the user can
# at least have some info on the source
if source is None:
if self.builder.builder_name != 'fallback':
remarks += [{
'checker' : 'hdlcc',
'line_number' : '',
'column' : '',
'filename' : '',
'error_number' : '',
'error_type' : 'W',
'error_message' : 'Path "%s" not found in project file' %
p.abspath(path)}]
self._logger.info("Path %s not found in the project file",
p.abspath(path))
cls = VhdlParser if getFileType(path) == 'vhdl' else VerilogParser
source = cls(path, library='undefined')
return source, remarks
def _buildSource(self, path, library, flags=None):
filetype = getFileType(path)
if filetype == 'vhdl':
return self._buildVhdl(path, library, flags)
elif filetype in ('verilog', 'systemverilog'):
return self._buildVerilog(path, library, flags)
else: # pragma: no cover
self._logger.error("Unknown file type %s for path '%s'",
filetype, path)
def _buildSource(self, path, library, flags=None):
filetype = getFileType(path)
if filetype == 'vhdl':
return self._buildVhdl(path, library, flags)
elif filetype in ('verilog', 'systemverilog'):
return self._buildVerilog(path, library, flags)
else: # pragma: no cover
self._logger.error("Unknown file type %s for path '%s'",
filetype, path)
def __init__(self, filename, library='work', flags=None):
self.filename = p.normpath(filename)
self.library = library
self.flags = flags if flags is not None else []
self._cache = {}
self._content = None
self._mtime = 0
self.filetype = getFileType(self.filename)
self._prev = None
self.abspath = p.abspath(filename)
def _buildVerilog(self, path, library, flags=None):
"Builds a Verilog/SystemVerilog file"
cmd = ['vlog', '-modelsimini', self._modelsim_ini, '-quiet',
'-work', p.join(self._target_folder, library)]
if getFileType(path) == 'systemverilog':
cmd += ['-sv']
if flags: # pragma: no cover
cmd += flags
cmd += self._getExtraFlags('verilog')
cmd += [path]
return self._subprocessRunner(cmd)
def _buildVerilog(self, path, library, flags=None):
"Builds a Verilog/SystemVerilog file"
cmd = ['vlog', '-modelsimini', self._modelsim_ini, '-quiet',
'-work', p.join(self._target_folder, library)]
if getFileType(path) == 'systemverilog':
cmd += ['-sv']
if flags: # pragma: no cover
cmd += flags
cmd += self._getExtraFlags('verilog')
cmd += [path]
return self._subprocessRunner(cmd)
def getSourceByPath(self, path):
"""
Get the source object, flags and any additional info to be displayed
"""
source = None
remarks = []
try:
source = self._config.getSourceByPath(path)
except KeyError:
pass
# If the source file was not found on the configuration file, add this
# as a remark.
# Also, create a source parser object with some library so the user can
# at least have some info on the source
if source is None:
if self.builder.builder_name != 'fallback':
remarks += [{
'checker':
'hdlcc',
'line_number':
'',
'column':
'',
'filename':
'',
'error_number':
'',
'error_type':
'W',
'error_message':
'Path "%s" not found in project file' % p.abspath(path)
}]
self._logger.info("Path %s not found in the project file",
p.abspath(path))
cls = VhdlParser if getFileType(path) == 'vhdl' else VerilogParser
source = cls(path, library='undefined')
return source, remarks
