def test006():
filename = p.join(VIM_HDL_EXAMPLES, 'another_library', 'foo.vhd')
it.assertTrue(it.project._msg_queue.empty())
code = open(filename, 'r').read().split('\n')
code[28] = '-- ' + code[28]
writeListToFile(filename, code)
records = it.project.getMessagesByPath(filename)
try:
it.assertNotIn(
{
'error_subtype': 'Style',
'line_number': 29,
'checker': 'HDL Code Checker/static',
'error_message': "constant 'ADDR_WIDTH' is never used",
'column': 14,
'error_type': 'W',
'error_number': '0',
'filename': None
}, records)
finally:
# Remove the comment we added
code[28] = code[28][3:]
writeListToFile(filename, code)
it.assertTrue(it.project._msg_queue.empty())
def setup():
it._code = [
"library ieee;",
"use ieee.std_logic_1164.all;",
"use ieee.std_logic_arith.all;",
"use ieee.std_logic_unsigned.all;",
"",
"library basic_library;",
"",
"package package_with_constants is",
"",
" constant SOME_INTEGER_CONSTANT : integer := 10;",
" constant SOME_STRING_CONSTANT : string := \"Hello\";",
"",
" constant SOME_STRING : string := " \
"basic_library.very_common_pkg.VIM_HDL_VERSION;",
"end;",
"",
"package body package_with_constants is",
"",
"end package body;",
]
writeListToFile(_FILENAME, it._code)
it._source_mtime = os.path.getmtime(_FILENAME)
def test():
# First create a project file with something in it
project_file = 'myproject.prj'
writeListToFile(project_file, [])
project = StandaloneProjectBuilder(project_file)
project._saveCache()
it.assertTrue(p.exists(p.join('.hdlcc', '.hdlcc.cache')),
"Cache filename not found")
open(p.join('.hdlcc', '.hdlcc.cache'), 'a').write("something\n")
project = StandaloneProjectBuilder(project_file)
found = False
while not project._msg_queue.empty():
severity, message = project._msg_queue.get()
_logger.info("Message found: [%s] %s", severity, message)
if message.startswith("Unable to recover cache from"):
found = True
break
if p.exists('.hdlcc'):
shutil.rmtree('.hdlcc')
it.assertTrue(found, "Failed to warn that cache recovering has failed")
it.assertTrue(project.builder.builder_name, 'Fallback')
def test():
# First create a project file with something in it
project_file = 'myproject.prj'
writeListToFile(project_file, [])
# Create a project object and force saving the cache
project = StandaloneProjectBuilder(project_file)
project._saveCache()
it.assertTrue(p.exists(p.join('.hdlcc', '.hdlcc.cache')),
"Cache filename not found")
# Now recreate the project and ensure it has recovered from the cache
del project
project = StandaloneProjectBuilder(project_file)
time.sleep(0.5)
found = False
while not project._msg_queue.empty():
severity, message = project._msg_queue.get()
_logger.info("Message found: [%s] %s", severity, message)
if message.startswith("Recovered cache from"):
found = True
break
if p.exists('.hdlcc'):
shutil.rmtree('.hdlcc')
it.assertTrue(found, "Failed to warn that cache recovering has worked")
it.assertTrue(project.builder.builder_name, 'MSimMock')
def setup():
it._code = [
"library ieee;",
"use ieee.std_logic_1164.all;",
"use ieee.std_logic_arith.all;",
"use ieee.std_logic_unsigned.all;",
"",
"library basic_library;",
"",
"package package_with_constants is",
"",
" constant SOME_INTEGER_CONSTANT : integer := 10;",
" constant SOME_STRING_CONSTANT : string := \"Hello\";",
"",
" constant SOME_STRING : string := " \
"basic_library.very_common_pkg.VIM_HDL_VERSION;",
"end;",
"",
"package body package_with_constants is",
"",
"end package body;",
]
writeListToFile(_FILENAME, it._code)
it._source_mtime = os.path.getmtime(_FILENAME)
def setup():
if os.path.exists(_FILENAME):
os.remove(_FILENAME)
it._code = [
"library ieee ;",
"use ieee.std_logic_1164.all;",
"USE IEEE.STD_LOGIC_ARITH.ALL;",
"",
"library work;",
"use work.package_with_constants;",
"",
"library lib1,lib2;",
"library lib3, lib4;",
"",
"entity clock_divider is",
" generic (",
" DIVIDER : integer := 10",
" );",
" port (",
" reset : in std_logic;",
" clk_input : in std_logic;",
" clk_output : out std_logic",
" );",
"end clock_divider;",
"",
"architecture clock_divider of clock_divider is",
"",
"begin",
"",
"end clock_divider;"]
writeListToFile(_FILENAME, it._code)
def setup():
if os.path.exists(_FILENAME):
os.remove(_FILENAME)
it._code = """
package msgPkg;
integer errCnt = 0;
integer warnCnt = 0;
endpackage
""".splitlines()
writeListToFile(_FILENAME, it._code)
def test011():
if not it.BUILDER_NAME:
_logger.info("Test requires a builder")
return
filenames = (p.join(VIM_HDL_EXAMPLES, 'basic_library',
'clock_divider.vhd'),
p.join(VIM_HDL_EXAMPLES, 'another_library',
'foo.vhd'))
# Count how many messages each source has
source_msgs = {}
for filename in filenames:
_logger.info("Getting messages for '%s'", filename)
source_msgs[filename] = \
it.project.getMessagesByPath(filename)
it.assertNotIn(
'E', [x['error_type'] for x in source_msgs[filename]])
_logger.info("Changing very_common_pkg to force rebuilding "
"synchronizer and another one I don't recall "
"right now")
very_common_pkg = p.join(VIM_HDL_EXAMPLES, 'basic_library',
'very_common_pkg.vhd')
code = open(very_common_pkg, 'r').read().split('\n')
writeListToFile(very_common_pkg,
code[:22] + \
[" constant ANOTHER_TEST_NOW : integer := 1;"] + \
code[22:])
try:
# The number of messages on all sources should not change
it.assertEquals(it.project.getMessagesByPath(very_common_pkg),
[])
for filename in filenames:
if source_msgs[filename]:
_logger.info(
"Source %s had the following messages:\n%s",
filename,
"\n".join([str(x) for x in source_msgs[filename]]))
else:
_logger.info("Source %s has no previous messages",
filename)
it.assertEquals(source_msgs[filename],
it.project.getMessagesByPath(filename))
finally:
_logger.info("Restoring previous content")
writeListToFile(very_common_pkg, code)
def setup():
if os.path.exists(_FILENAME):
os.remove(_FILENAME)
it._code = """
package msgPkg;
integer errCnt = 0;
integer warnCnt = 0;
endpackage
""".splitlines()
writeListToFile(_FILENAME, it._code)
def setup():
it.project_filename = 'test.prj'
it.lib_path = p.join(TEST_SUPPORT_PATH, 'vim-hdl-examples')
it.sources = [
('work', p.join('another_library', 'foo.vhd')),
('work', p.join('basic_library', 'clock_divider.vhd'))]
writeListToFile(
it.project_filename,
["vhdl %s %s" % (lib, path) for lib, path in it.sources])
it.parser = ConfigParser(it.project_filename)
def setup():
it.project_filename = 'test.prj'
it.lib_path = p.join(TEST_SUPPORT_PATH, 'vim-hdl-examples')
it.sources = [('work', p.join('another_library', 'foo.vhd')),
('work', p.join('basic_library',
'clock_divider.vhd'))]
writeListToFile(
it.project_filename,
["vhdl %s %s" % (lib, path) for lib, path in it.sources])
it.parser = ConfigParser(it.project_filename)
def setup():
if os.path.exists(_FILENAME):
os.remove(_FILENAME)
it._code = """
module clock_divider
#(parameter DIVISION = 5)
(// Usual ports
input clk,
input rst,
// Output clock divided
output clk_div);
""".splitlines()
writeListToFile(_FILENAME, it._code)
def setup():
if os.path.exists(_FILENAME):
os.remove(_FILENAME)
it._code = """
module clock_divider
#(parameter DIVISION = 5)
(// Usual ports
input clk,
input rst,
// Output clock divided
output clk_div);
""".splitlines()
writeListToFile(_FILENAME, it._code)
def test():
code = list(it._code)
code.insert(0, ' use work.another_package;')
writeListToFile(_FILENAME, code)
dependencies = it.source.getDependencies()
_logger.info("Dependencies: %s", dependencies)
it.assertNotEqual(dependencies, None, "No dependencies found")
it.assertItemsEqual(
[{'unit': 'std_logic_1164', 'library': 'ieee'},
{'unit': 'std_logic_arith', 'library': 'ieee'},
{'unit': 'another_package', 'library': 'work'},
{'unit': 'package_with_constants', 'library': 'work'}],
dependencies)
def getSourcesFrom(sources=None):
prj_content = []
if sources is None:
sources = list(it.sources)
for lib, path in sources:
prj_content += ["vhdl %s %s" % (lib, path)]
writeListToFile(it.project_filename, prj_content)
result = {}
for source in it.parser.getSources():
result[source.filename] = source
return result
def getSourcesFrom(sources=None):
prj_content = []
if sources is None:
sources = list(it.sources)
for lib, path in sources:
prj_content += ["vhdl %s %s" % (lib, path)]
writeListToFile(it.project_filename, prj_content)
result = {}
for source in it.parser.getSources():
result[source.filename] = source
return result
def setup():
if os.path.exists(_FILENAME):
os.remove(_FILENAME)
it._code = [
"library ieee ;", "use ieee.std_logic_1164.all;",
"USE IEEE.STD_LOGIC_ARITH.ALL;", "", "library work;",
"use work.package_with_constants;", "", "library lib1,lib2;",
"library lib3, lib4;", "", "entity clock_divider is",
" generic (", " DIVIDER : integer := 10", " );",
" port (", " reset : in std_logic;",
" clk_input : in std_logic;",
" clk_output : out std_logic", " );",
"end clock_divider;", "",
"architecture clock_divider of clock_divider is", "", "begin",
"", "end clock_divider;"
]
writeListToFile(_FILENAME, it._code)
def test():
code = list(it._code)
code.insert(0, 'library remove_me;')
writeListToFile(_FILENAME, code)
dependencies = it.source.getDependencies()
if dependencies:
_logger.info("Dependencies:")
for dep in dependencies:
_logger.info(str(dep))
else:
_logger.warning("No dependencies found")
it.assertNotEqual(dependencies, None, "No dependencies found")
it.assertItemsEqual(
[{'unit': 'std_logic_1164', 'library': 'ieee'},
{'unit': 'std_logic_arith', 'library': 'ieee'},
{'unit': 'package_with_constants', 'library': 'work'}],
dependencies)
def test009():
if not it.PROJECT_FILE:
_logger.info("Requires a valid project file")
return
filename = 'some_file.vhd'
writeListToFile(filename, ['library some_lib;'])
it.assertTrue(it.project._msg_queue.empty())
records = it.project.getMessagesByPath(filename)
_logger.info("Records found:")
for record in records:
_logger.info(record)
it.assertIn(
{
'checker':
'hdlcc',
'line_number':
'',
'column':
'',
'filename':
'',
'error_number':
'',
'error_type':
'W',
'error_message':
'Path "%s" not found in '
'project file' % p.abspath(filename)
}, records)
# The builder should find other issues as well...
it.assertTrue(
len(records) > 1,
"It was expected that the builder added some "
"message here indicating an error")
it.assertTrue(it.project._msg_queue.empty())
def test():
code = list(it._code)
code.insert(0, ' use work.another_package;')
writeListToFile(_FILENAME, code)
dependencies = it.source.getDependencies()
_logger.info("Dependencies: %s", dependencies)
it.assertNotEqual(dependencies, None, "No dependencies found")
it.assertItemsEqual([{
'unit': 'std_logic_1164',
'library': 'ieee'
}, {
'unit': 'std_logic_arith',
'library': 'ieee'
}, {
'unit': 'another_package',
'library': 'work'
}, {
'unit': 'package_with_constants',
'library': 'work'
}], dependencies)
def test():
code = list(it._code)
code.insert(0, 'library remove_me;')
writeListToFile(_FILENAME, code)
dependencies = it.source.getDependencies()
if dependencies:
_logger.info("Dependencies:")
for dep in dependencies:
_logger.info(str(dep))
else:
_logger.warning("No dependencies found")
it.assertNotEqual(dependencies, None, "No dependencies found")
it.assertItemsEqual([{
'unit': 'std_logic_1164',
'library': 'ieee'
}, {
'unit': 'std_logic_arith',
'library': 'ieee'
}, {
'unit': 'package_with_constants',
'library': 'work'
}], dependencies)
def test005c():
filename = 'some_file.vhd'
writeListToFile(filename, [
"entity some_entity is end;",
])
content = "\n".join([
"library work;", "use work.all;", "entity some_entity is end;"
])
it.assertTrue(it.project._msg_queue.empty())
records = it.project.getMessagesWithText(filename, content)
_logger.debug("Records received:")
for record in records:
_logger.debug("- %s", record)
# Check that all records point to the original filename and
# remove them from the records so it's easier to compare
# the remaining fields
for record in records:
record_filename = record.pop('filename')
if record_filename:
it.assertTrue(samefile(filename, record_filename))
if it.project.builder.builder_name in ('msim', 'ghdl', 'xvhdl'):
it.assertItemsEqual([{
'error_type': 'W',
'checker': 'HDL Code Checker/static',
'error_message':
"Declaration of library 'work' can be omitted",
'column': 9,
'error_subtype': 'Style',
'error_number': '0',
'line_number': 1
}, {
'error_type':
'W',
'checker':
'hdlcc',
'error_message':
'Path "%s" not found in project file' %
p.abspath(filename),
'column':
'',
'error_number':
'',
'line_number':
''
}], records)
else:
it.assertItemsEqual([{
'error_type': 'W',
'checker': 'HDL Code Checker/static',
'error_message':
"Declaration of library 'work' can be omitted",
'column': 9,
'error_subtype': 'Style',
'error_number': '0',
'line_number': 1
}], records)
it.assertTrue(it.project._msg_queue.empty())
