def runtest():
# Even though this is a TX-only test, both PHYs are needed in order to drive the mode pins for RGMII
# Test 100 MBit - MII XS1
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker,
test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False)
if run_on(phy='mii', clk='25Mhz', mac='standard', arch='xs1'):
do_test('standard', 'xs1', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt', arch='xs1'):
do_test('rt', 'xs1', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt_hp', arch='xs1'):
do_test('rt_hp', 'xs1', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - MII XS2
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker,
test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False)
if run_on(phy='mii', clk='25Mhz', mac='standard', arch='xs2'):
do_test('standard', 'xs2', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt', arch='xs2'):
do_test('rt', 'xs2', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt_hp', arch='xs2'):
do_test('rt_hp', 'xs2', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - RGMII
(rx_clk_25,
rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz,
packet_fn=packet_checker,
test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz,
do_timeout=False)
if run_on(phy='rgmii', clk='25Mhz', mac='rt', arch='xs2'):
do_test('rt', 'xs2', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
if run_on(phy='rgmii', clk='25Mhz', mac='rt_hp', arch='xs2'):
do_test('rt_hp', 'xs2', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
# Test 1000 MBit - RGMII
(rx_clk_125,
rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_125MHz,
packet_fn=packet_checker,
test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_125, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_125MHz,
do_timeout=False)
if run_on(phy='rgmii', clk='125Mhz', mac='rt', arch='xs2'):
do_test('rt', 'xs2', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
if run_on(phy='rgmii', clk='125Mhz', mac='rt_hp', arch='xs2'):
do_test('rt_hp', 'xs2', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
def runtest():
# Test 100 MBit - MII
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker)
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False, verbose=args.verbose)
if run_on(phy='mii', clk='25Mhz', mac='standard'):
do_test('standard', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt_hp'):
do_test('rt_hp', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - RGMII
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz, packet_fn=packet_checker)
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz, do_timeout=False,
verbose=args.verbose)
if run_on(phy='rgmii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
if run_on(phy='rgmii', clk='25Mhz', mac='rt_hp'):
do_test('rt_hp', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
# Test 1000 MBit - RGMII
(rx_clk_125, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_125MHz, packet_fn=packet_checker)
(tx_clk_125, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_125MHz, do_timeout=False,
verbose=args.verbose)
if run_on(phy='rgmii', clk='125Mhz', mac='rt'):
do_test('rt', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
if run_on(phy='rgmii', clk='125Mhz', mac='rt_hp'):
do_test('rt_hp', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
def runtest():
random.seed(100)
# Test 100 MBit - MII
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker,
test_ctrl=test_ctrl)
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False, complete_fn=set_tx_complete,
verbose=args.verbose, dut_exit_time=200000)
if run_on(phy='mii', clk='25Mhz', mac='standard'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
do_test('standard', rx_clk_25, rx_mii, tx_clk_25, tx_mii, seed)
if run_on(phy='mii', clk='25Mhz', mac='rt'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
do_test('rt', rx_clk_25, rx_mii, tx_clk_25, tx_mii, seed)
if run_on(phy='mii', clk='25Mhz', mac='rt_hp'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
do_test('rt_hp', rx_clk_25, rx_mii, tx_clk_25, tx_mii, seed)
# Test 100 MBit - RGMII
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz, packet_fn=packet_checker,
test_ctrl=test_ctrl)
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz, do_timeout=False,
complete_fn=set_tx_complete, verbose=args.verbose,
dut_exit_time=200000)
if run_on(phy='rgmii', clk='25Mhz', mac='rt_hp'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
do_test('rt_hp', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii, seed)
def runtest():
# Even though this is a TX-only test, both PHYs are needed in order to drive the mode pins for RGMII
# Test 100 MBit - MII
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker,
verbose=args.verbose)
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False)
if run_on(phy='mii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - RGMII
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz,
packet_fn=packet_checker,
verbose=args.verbose)
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz,
do_timeout=False)
if run_on(phy='rgmii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
# Test 1000 MBit - RGMII
(rx_clk_125, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_125MHz,
packet_fn=packet_checker,
verbose=args.verbose)
(tx_clk_125, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_125MHz,
do_timeout=False)
if run_on(phy='rgmii', clk='125Mhz', mac='rt'):
do_test('rt', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
def runall_rx(test_fn):
# Test 100 MBit
for arch in ['xs1', 'xs2']:
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=check_received_packet)
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(verbose=args.verbose, test_ctrl="tile[0]:XS1_PORT_1A")
if run_on(phy='mii', clk='25Mhz', mac='standard', arch=arch):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
test_fn('standard', arch, rx_clk_25, rx_mii, tx_clk_25, tx_mii, seed)
# Only run on the rt MAC. The HP queue does not support lots of backpressure
# as it expects the client to consume packets or else it locks up and
# everything goes wrong
if run_on(phy='mii', clk='25Mhz', mac='rt', arch=arch):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
test_fn('rt', arch, rx_clk_25, rx_mii, tx_clk_25, tx_mii, seed)
# Test 100 MBit - RGMII - only supported on XS2
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz, packet_fn=check_received_packet)
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz, verbose=args.verbose, test_ctrl="tile[0]:XS1_PORT_1A")
if run_on(phy='rgmii', clk='25Mhz', mac='rt', arch='xs2'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
test_fn('rt', 'xs2', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii, seed)
# Test 1000 MBit - RGMII - only supported on XS2
(rx_clk_125, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_125MHz, packet_fn=check_received_packet)
(tx_clk_125, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_125MHz, verbose=args.verbose, test_ctrl="tile[0]:XS1_PORT_1A")
if run_on(phy='rgmii', clk='125Mhz', mac='rt', arch='xs2'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
test_fn('rt', 'xs2', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii, seed)
def runtest():
random.seed(100)
# Test 100 MBit - MII
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker,
test_ctrl=test_ctrl)
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False, complete_fn=set_tx_complete,
verbose=args.verbose, dut_exit_time=200000)
if run_on(phy='mii', clk='25Mhz', mac='standard'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
do_test('standard', rx_clk_25, rx_mii, tx_clk_25, tx_mii, seed)
if run_on(phy='mii', clk='25Mhz', mac='rt'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
do_test('rt', rx_clk_25, rx_mii, tx_clk_25, tx_mii, seed)
if run_on(phy='mii', clk='25Mhz', mac='rt_hp'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
do_test('rt_hp', rx_clk_25, rx_mii, tx_clk_25, tx_mii, seed)
# Test 100 MBit - RGMII
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz, packet_fn=packet_checker,
test_ctrl=test_ctrl)
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz, do_timeout=False,
complete_fn=set_tx_complete, verbose=args.verbose,
dut_exit_time=200000)
if run_on(phy='rgmii', clk='25Mhz', mac='rt_hp'):
seed = args.seed if args.seed else random.randint(0, sys.maxint)
do_test('rt_hp', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii, seed)
def runtest():
# Test 100 MBit - MII
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker)
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False,
verbose=args.verbose)
if run_on(phy='mii', clk='25Mhz', mac='standard'):
do_test('standard', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt_hp'):
do_test('rt_hp', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - RGMII
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz,
packet_fn=packet_checker)
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz,
do_timeout=False,
verbose=args.verbose)
if run_on(phy='rgmii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
if run_on(phy='rgmii', clk='25Mhz', mac='rt_hp'):
do_test('rt_hp', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
# Test 1000 MBit - RGMII
(rx_clk_125, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_125MHz,
packet_fn=packet_checker)
(tx_clk_125, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_125MHz,
do_timeout=False,
verbose=args.verbose)
if run_on(phy='rgmii', clk='125Mhz', mac='rt'):
do_test('rt', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
if run_on(phy='rgmii', clk='125Mhz', mac='rt_hp'):
do_test('rt_hp', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
def runtest():
# Even though this is a TX-only test, both PHYs are needed in order to drive the mode pins for RGMII
# Test 100 MBit - MII XS1
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker, test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False)
if run_on(phy='mii', clk='25Mhz', mac='standard', arch='xs1'):
do_test('standard', 'xs1', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt', arch='xs1'):
do_test('rt', 'xs1', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt_hp', arch='xs1'):
do_test('rt_hp', 'xs1', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - MII XS2
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker, test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False)
if run_on(phy='mii', clk='25Mhz', mac='standard', arch='xs2'):
do_test('standard', 'xs2', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt', arch='xs2'):
do_test('rt', 'xs2', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
if run_on(phy='mii', clk='25Mhz', mac='rt_hp', arch='xs2'):
do_test('rt_hp', 'xs2', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - RGMII
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz, packet_fn=packet_checker,
test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz, do_timeout=False)
if run_on(phy='rgmii', clk='25Mhz', mac='rt', arch='xs2'):
do_test('rt', 'xs2', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
if run_on(phy='rgmii', clk='25Mhz', mac='rt_hp', arch='xs2'):
do_test('rt_hp', 'xs2', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
# Test 1000 MBit - RGMII
(rx_clk_125, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_125MHz, packet_fn=packet_checker,
test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_125, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_125MHz, do_timeout=False)
if run_on(phy='rgmii', clk='125Mhz', mac='rt', arch='xs2'):
do_test('rt', 'xs2', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
if run_on(phy='rgmii', clk='125Mhz', mac='rt_hp', arch='xs2'):
do_test('rt_hp', 'xs2', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
def runtest():
# Even though this is a TX-only test, both PHYs are needed in order to drive the mode pins for RGMII
# Test 100 MBit - MII
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker, test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(dut_exit_time=200000)
if run_on(phy='mii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - RGMII
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz, packet_fn=packet_checker,
test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz, dut_exit_time=200000)
if run_on(phy='rgmii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
# Test 1000 MBit - RGMII
(rx_clk_125, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_125MHz, packet_fn=packet_checker,
test_ctrl='tile[0]:XS1_PORT_1C')
(tx_clk_125, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_125MHz, dut_exit_time=300000)
if run_on(phy='rgmii', clk='125Mhz', mac='rt'):
do_test('rt', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)
def runtest():
# Even though this is a TX-only test, both PHYs are needed in order to drive the mode pins for RGMII
# Test 100 MBit - MII
(rx_clk_25, rx_mii) = get_mii_rx_clk_phy(packet_fn=packet_checker, verbose=args.verbose)
(tx_clk_25, tx_mii) = get_mii_tx_clk_phy(do_timeout=False)
if run_on(phy='mii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_mii, tx_clk_25, tx_mii)
# Test 100 MBit - RGMII
(rx_clk_25, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_25MHz, packet_fn=packet_checker,
verbose=args.verbose)
(tx_clk_25, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_25MHz, do_timeout=False)
if run_on(phy='rgmii', clk='25Mhz', mac='rt'):
do_test('rt', rx_clk_25, rx_rgmii, tx_clk_25, tx_rgmii)
# Test 1000 MBit - RGMII
(rx_clk_125, rx_rgmii) = get_rgmii_rx_clk_phy(Clock.CLK_125MHz, packet_fn=packet_checker,
verbose=args.verbose)
(tx_clk_125, tx_rgmii) = get_rgmii_tx_clk_phy(Clock.CLK_125MHz, do_timeout=False)
if run_on(phy='rgmii', clk='125Mhz', mac='rt'):
do_test('rt', rx_clk_125, rx_rgmii, tx_clk_125, tx_rgmii)