def mergeSplitsOnInterfaces(root: LNode): """ collect all split/concatenation nodes and group them by target interface """ for ch in root.children: if ch.children: mergeSplitsOnInterfaces(ch) ctx = MergeSplitsOnInterfacesCtx() for ch in root.children: srcPorts = None try: if ch.name == "CONCAT": p = single(ch.east, lambda x: True) e = single(p.outgoingEdges, lambda x: True) srcPorts = e.dsts elif ch.name == "SLICE": p = single(ch.west, lambda x: True) e = single(p.incomingEdges, lambda x: True) srcPorts = e.srcs except (DuplicitValueExc, NoValueExc): continue if srcPorts is not None: for srcPort in srcPorts: if isinstance(srcPort.parent, LPort): # only for non primitive ports rootPort = getRootIntfPort(srcPort) ctx.register(rootPort, ch, e) # join them if it is possible for srcPort, splitsAndConcats in ctx.iterPortSplits(): if len(splitsAndConcats) <= 1: continue name = "SPLIT" if srcPort.direction == PortType.OUTPUT else "CONCAT" newSplitNode = root.addNode(name=name, cls="Operator") copyPort(srcPort, newSplitNode, True, "") n = splitsAndConcats[0][0] for i in range(max(len(n.west), len(n.east))): copyPort(srcPort, newSplitNode, False, f"[{i:d}]") reconnectPorts(root, srcPort, splitsAndConcats, newSplitNode)
def _boundIntfSignalToEntity(self, interface, inftToPortDict): portItem = single(self._entity.ports, lambda x : x._interface == interface) interface._boundedEntityPort = portItem d = INTF_DIRECTION.asDirection(interface._direction) if d == DIRECTION.INOUT: portItem.direction = DIRECTION.INOUT if portItem.direction != d: # print(self._entity) # print(self._architecture) raise IntfLvlConfErr("Unit %s: Port %s does not have direction defined by interface %s, is %s should be %s" % (self._name, portItem.name, repr(interface), portItem.direction, d))
def getPort(entity, portName): return single(entity.ports, lambda x: x.name == portName)
def findPort(self, logName): logName = logName.lower() p = single(self.port, lambda x: x.logName.lower() == logName) return p
def getPort(entity, portName): return single(entity.ports, lambda x: x.name == portName)
def _tryToExtractByName(self, prefix, ports): """ :return: self if extraction was successful :raise InterfaceIncompatibilityExc: if this interface with this prefix does not fit for this entity """ if self._interfaces: # extract subinterfaces and propagate params allDirMatch = True noneDirMatch = True if hasattr(self, "_name") and self._name != '': prefix += self._name + self._NAME_SEPARATOR try: for intf in self._interfaces: intf._tryToExtractByName(prefix, ports) if intf._interfaces: dirMatches = intf._direction == INTF_DIRECTION.MASTER else: dirMatches = intf._boundedEntityPort.direction == intf._masterDir allDirMatch = allDirMatch and dirMatches noneDirMatch = noneDirMatch and not dirMatches except InterfaceIncompatibilityExc as e: for intf in self._interfaces: intf._unExtrac() raise e if allDirMatch: self._direction = INTF_DIRECTION.MASTER elif noneDirMatch: self._direction = INTF_DIRECTION.SLAVE else: self._unExtrac() raise InterfaceIncompatibilityExc("Direction mismatch") else: # extract signal(Signal , etc.) # collect all possible names intfNames = [] if hasattr(self, "_name"): intfNames.append(self._name) intfNames.extend(self._alternativeNames) # try find suitable portItem in entity port for n in intfNames: name = prefix + n try: self._boundedEntityPort = single(ports, lambda p : matchIgnorecase(p.name, name)) break except NoValueExc as e: continue if not hasattr(self, "_boundedEntityPort"): self._unExtrac() raise InterfaceIncompatibilityExc("Missing " + prefix + n) self._extractDtype() # assign references to hdl objects self._boundedEntityPort._interface = self # resolve direction dirMatches = self._boundedEntityPort.direction == self._masterDir if dirMatches: self._direction = INTF_DIRECTION.MASTER else: self._direction = INTF_DIRECTION.SLAVE return self