def synthesize(self, name, interfaces, targetPlatform):
"""
Build Entity and Architecture instance out of netlist representation
"""
ent = Entity(name)
ent._name = name + "_inst" # instance name
# create generics
for _, v in self.params.items():
ent.generics.append(v)
# interface set for faster lookup
if isinstance(interfaces, set):
intfSet = interfaces
else:
intfSet = set(interfaces)
# create ports
for s in interfaces:
pi = portItemfromSignal(s, ent)
pi.registerInternSig(s)
ent.ports.append(pi)
s.hidden = False
removeUnconnectedSignals(self)
markVisibilityOfSignals(self, name, self.signals, intfSet)
for proc in targetPlatform.beforeHdlArchGeneration:
proc(self)
arch = Architecture(ent)
for p in statements_to_HWProcesses(self.statements):
arch.processes.append(p)
# add signals, variables etc. in architecture
for s in self.signals:
if s not in intfSet and not s.hidden:
arch.variables.append(s)
# instantiate subUnits in architecture
for u in self.subUnits:
arch.componentInstances.append(u)
# add components in architecture
for su in distinctBy(self.subUnits, lambda x: x.name):
arch.components.append(su)
self.synthesised = True
return [ent, arch]
def netlistToVhdlStr(name: str, netlist: RtlNetlist,
interfaces: Dict[RtlSignal, DIRECTION]):
name_scope = NameScope(None, name, True)
buff = StringIO()
store_manager = SaveToStream(Vhdl2008Serializer, buff)
netlist.create_HdlModuleDec(name, store_manager, {})
netlist.interfaces = interfaces
for s, d in interfaces.items():
s._interface = True
pi = portItemfromSignal(s, netlist, d)
# port of current top component
s.name = name_scope.checked_name(s.name, s)
pi.connectInternSig(s)
netlist.ent.ports.append(pi)
netlist.ent.ports.sort(key=lambda x: x.name)
netlist.create_HdlModuleDef(DummyPlatform(), store_manager)
store_manager.write(netlist.arch)
return buff.getvalue()
def synthesize(self, name, interfaces):
"""
Build Entity and architecture out of netlist representation
"""
ent = Entity(name)
ent._name = name + "_inst" # instance name
# create generics
for _, v in self.globals.items():
ent.generics.append(v)
# create ports
for s in interfaces:
pi = portItemfromSignal(s, ent)
pi.reigsterInternSig(s)
ent.ports.append(pi)
removeUnconnectedSignals(self)
arch = Architecture(ent)
for p in self.buildProcessesOutOfAssignments():
arch.processes.append(p)
# add signals, variables etc. in architecture
for s in self.signals:
if s not in interfaces and not s.hidden:
arch.variables.append(s)
# instanciate subUnits in architecture
for u in self.subUnits:
arch.componentInstances.append(u)
# add components in architecture
for su in distinctBy(self.subUnits, lambda x: x.name):
arch.components.append(su)
self.synthesised = True
return [ent, arch]
def _signalsForInterface(self,
ctx: RtlNetlist,
res: Optional[Dict[RtlSignal, DIRECTION]],
name_scope: Optional[NameScope],
prefix='',
typeTransform=None,
reverse_dir=False):
"""
Generate RtlSignal _sig and HdlPortInstance _hdl_port
for each interface which has no subinterface
:note: if already has _sig return use it instead
:param ctx: instance of RtlNetlist where signals should be created
:param res: output dictionary where result should be stored
:param prefix: name prefix for created signals
:param name_scope: name scope used to check colisions on port names
if this a current top (every component is checked
when it is seen first time)
:param typeTransform: optional function (type) returns modified type
for signal
"""
if self._interfaces:
for intf in self._interfaces:
intf._signalsForInterface(ctx,
res,
name_scope,
prefix=prefix,
typeTransform=typeTransform,
reverse_dir=reverse_dir)
else:
assert self._sig is None, self
t = self._dtype
if typeTransform is not None:
t = typeTransform(t)
s = ctx.sig(prefix + self._getPhysicalName(), t)
s._interface = self
self._sig = s
if self._isExtern:
d = INTF_DIRECTION.asDirection(self._direction)
u = ctx.parent
if reverse_dir:
d = DIRECTION.opposite(d)
assert self._hdl_port is None, (
"Now creating a hdl interface for top"
" it but seems that it was already created")
if res is not None:
res[s] = d
if reverse_dir:
pi = portItemfromSignal(s, u, d)
# port of current top component
s.name = name_scope.checked_name(s.name, s)
pi.connectInternSig(s)
ctx.ent.ports.append(pi)
else:
pi = self._hdl_port
# port of some subcomponent which names were already checked
pi.connectOuterSig(s)
self._hdl_port = pi
