def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.drivers = HObjList(
AxiWDatapumpIntf()
for _ in range(int(self.DRIVER_CNT)))
self.wDatapump = AxiWDatapumpIntf()._m()
self.DRIVER_INDEX_WIDTH = log2ceil(self.DRIVER_CNT).val
fW = self.orderInfoFifoW = HandshakedFifo(Handshaked)
fAck = self.orderInfoFifoAck = HandshakedFifo(Handshaked)
for f in [fW, fAck]:
f.DEPTH.set(self.MAX_TRANS_OVERLAP)
f.DATA_WIDTH.set(self.DRIVER_INDEX_WIDTH)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
# read interface for datapump
# interface which sending requests to download addr of next block
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(
1) # because we are downloading only addres of next block
# write interface for datapump
self.wDatapump = AxiWDatapumpIntf()._m()
self.wDatapump.MAX_LEN.set(self.BUFFER_CAPACITY // 2)
assert self.BUFFER_CAPACITY <= self.ITEMS_IN_BLOCK
# interface for items which should be written into list
self.dataIn = Handshaked()
# interface to control internal register
a = self.baseAddr = RegCntrl()
a._replaceParam(a.DATA_WIDTH, self.ADDR_WIDTH)
self.rdPtr = RegCntrl()
self.wrPtr = RegCntrl()
for ptr in [self.rdPtr, self.wrPtr]:
ptr._replaceParam(ptr.DATA_WIDTH, self.PTR_WIDTH)
f = self.dataFifo = HandshakedFifo(Handshaked)
f.EXPORT_SIZE.set(True)
f.DATA_WIDTH.set(self.DATA_WIDTH)
f.DEPTH.set(self.BUFFER_CAPACITY)
self.ALIGN_BITS = log2ceil(self.DATA_WIDTH // 8).val
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.dp = Axi_wDatapump(axiAddrCls=Axi3_addr)
self.ic = WStrictOrderInterconnect()
self.aw = Axi3_addr()._m()
self.w = Axi4_w()._m()
self.b = Axi4_b()
self.drivers = HObjList(AxiWDatapumpIntf()
for _ in range(int(self.DRIVER_CNT)))
def _declr(self):
super()._declr() # add clk, rst, axi addr channel and req channel
with self._paramsShared():
self.w = self._axiWCls()._m()
self.b = Axi4_b()
self.errorWrite = Signal()._m()
self.driver = AxiWDatapumpIntf()
with self._paramsShared():
# fifo for id propagation and frame splitting on axi.w channel
wf = self.writeInfoFifo = HandshakedFifo(WFifoIntf)
wf.ID_WIDTH.set(self.ID_WIDTH)
wf.DEPTH.set(self.MAX_TRANS_OVERLAP)
# fifo for propagation of end of frame from axi.b channel
bf = self.bInfoFifo = HandshakedFifo(BFifoIntf)
bf.DEPTH.set(self.MAX_TRANS_OVERLAP)
def _declr(self):
addClkRstn(self)
self.parseTemplate()
self.dataIn = StructIntf(self._structT,
self._createInterfaceForField)
s = self.set = Handshaked() # data signal is addr of structure to write
s._replaceParam(s.DATA_WIDTH, self.ADDR_WIDTH)
# write ack from slave
self.writeAck = HandshakeSync()._m()
with self._paramsShared():
# interface for communication with datapump
self.wDatapump = AxiWDatapumpIntf()._m()
self.wDatapump.MAX_LEN.set(self.maxWordIndex() + 1)
self.frameAssember = AxiS_frameForge(self._structT,
tmpl=self._tmpl,
frames=self._frames)
def _declr(self):
addClkRstn(self)
self.items = Handshaked()
self.items.DATA_WIDTH.set(self.SIZE_WIDTH)
with self._paramsShared():
self.wDatapump = AxiWDatapumpIntf()._m()
self.uploaded = VectSignal(16)._m()
self.baseAddr = RegCntrl()
self.baseAddr.DATA_WIDTH.set(self.ADDR_WIDTH)
self.buff_remain = VectSignal(16)._m()
b = HandshakedFifo(Handshaked)
b.DATA_WIDTH.set(self.SIZE_WIDTH)
b.EXPORT_SIZE.set(True)
b.DEPTH.set(self.BUFF_DEPTH)
self.buff = b
def _config(self):
self.DRIVER_CNT = Param(2)
self.MAX_TRANS_OVERLAP = Param(16)
AxiWDatapumpIntf._config(self)