def setUpCrc(self,
poly,
dataWidth=None,
refin=None,
refout=None,
initval=None,
finxor=None,
bigendian=False):
if dataWidth is None:
dataWidth = poly.WIDTH
u = self.u = CrcComb()
u.setConfig(poly)
u.DATA_WIDTH = dataWidth
if initval is not None:
u.INIT = Bits(poly.WIDTH).from_py(initval)
if refin is not None:
u.REFIN = refin
if refout is not None:
u.REFOUT = refout
if finxor is not None:
u.XOROUT = Bits(poly.WIDTH).from_py(finxor)
u.IN_IS_BIGENDIAN = bigendian
self.compileSimAndStart(u)
return u
def setUpCrc(self,
poly,
dataWidth=None,
refin=False,
refout=False,
initval=0,
finxor=0):
if dataWidth is None:
dataWidth = poly.WIDTH
u = self.u = CrcComb()
self.DATA_WIDTH = dataWidth
self.POLY_WIDTH = poly.WIDTH
u.DATA_WIDTH.set(dataWidth)
u.POLY_WIDTH.set(poly.WIDTH)
u.POLY.set(vec(poly.POLY, poly.WIDTH))
u.INIT.set(vec(initval, poly.WIDTH))
u.REFIN.set(refin)
u.REFOUT.set(refout)
u.XOROUT.set(vec(finxor, poly.WIDTH))
self.prepareUnit(u)
return u
def _declr(self):
addClkRstn(self)
assert int(self.KEY_WIDTH) > 0
assert int(self.DATA_WIDTH) >= 0
assert int(self.ITEMS_CNT) > 1
self.HASH_WITH = log2ceil(self.ITEMS_CNT).val
assert self.HASH_WITH < int(self.KEY_WIDTH), (
"It makes no sense to use hash table when you can use key directly as index",
self.HASH_WITH, self.KEY_WIDTH)
with self._paramsShared():
self.insert = InsertIntf()
self.insert.HASH_WIDTH.set(self.HASH_WITH)
self.lookup = LookupKeyIntf()
self.lookupRes = LookupResultIntf()._m()
self.lookupRes.HASH_WIDTH.set(self.HASH_WITH)
t = self.table = RamSingleClock()
t.PORT_CNT.set(1)
t.ADDR_WIDTH.set(log2ceil(self.ITEMS_CNT))
t.DATA_WIDTH.set(self.KEY_WIDTH + self.DATA_WIDTH +
1) # +1 for vldFlag
tc = self.tableConnector = RamAsHs()
tc.ADDR_WIDTH.set(t.ADDR_WIDTH.get())
tc.DATA_WIDTH.set(t.DATA_WIDTH.get())
hashWidth = max(int(self.KEY_WIDTH), int(self.HASH_WITH))
h = self.hash = CrcComb()
h.DATA_WIDTH.set(hashWidth)
h.setConfig(self.POLYNOME)
h.POLY_WIDTH.set(hashWidth)
def test_CrcComb(self):
u = CrcComb()
u.DATA_WIDTH = 8
convert(u)