def test_itIsPossibleToSerializeIpcores(self):
f = Fifo()
f.DEPTH = 16
en0 = AxiS_en()
en0.USE_STRB = True
en0.USE_KEEP = True
en0.ID_WIDTH = 8
en0.DEST_WIDTH = 4
en0.USER_WIDTH = 12
u0 = SimpleUnitWithParam()
u0.DATA_WIDTH = 2
u1 = SimpleUnitWithParam()
u1.DATA_WIDTH = 3
u_with_hdl_params = MultiConfigUnitWrapper([u0, u1])
testUnits = [
AxiS_en(),
en0,
AxiLiteEndpoint(HStruct((uint64_t, "f0"), (uint64_t[10], "arr0"))),
I2cMasterBitCtrl(),
f,
Axi4streamToMem(),
IpCoreIntfTest(),
u_with_hdl_params,
]
for u in testUnits:
serializeAsIpcore(u, folderName=self.test_dir)
def test_stm_enclosure_consystency(self):
u = I2cMasterBitCtrl()
self.check_consystency(u)
# test there is not a latch
for stm in u._ctx.statements:
if not stm._is_completly_event_dependent:
diff = stm._enclosed_for.symmetric_difference(stm._outputs)
self.assertEqual(diff, set(), "\n%r" % stm)
def test_stm_enclosure_consystency(self):
u = I2cMasterBitCtrl()
self.check_consystency(u)
# test if there is not a latch
for stm in u._ctx.statements:
if stm._event_dependent_from_branch != 0:
diff = stm._enclosed_for.symmetric_difference(stm._outputs)
self.assertEqual(diff, set(), f"\n{stm}")
def test_itIsPossibleToSerializeIpcores(self):
f = Fifo()
f.DEPTH.set(16)
en0 = AxiS_en()
en0.USE_STRB.set(True)
en0.USE_KEEP.set(True)
en0.ID_WIDTH.set(8)
en0.DEST_WIDTH.set(4)
en0.USER_WIDTH.set(12)
testUnits = [
AxiS_en(), en0,
AxiLiteEndpoint(HStruct((uint64_t, "f0"), (uint64_t[10], "arr0"))),
I2cMasterBitCtrl(), f,
Axi4streamToMem(),
IpCoreIntfTest()
]
for u in testUnits:
serializeAsIpcore(u, folderName=self.test_dir)
def setUpClass(cls):
cls.u = I2cMasterBitCtrl()
cls.compileSim(cls.u)
def test_I2cMasterBitCtrl(self):
u = I2cMasterBitCtrl()
convert(u)
def setUp(self):
self.u = I2cMasterBitCtrl()
self.prepareUnit(self.u)