def _set_datarate(self, rate):
'''Set the data rate in the CCR.
Datarate should be one of:
00 = 500kbits/s
01 = 300kbits/s
10 = 250kbits/s
11 - 1Mbits/s
500kbits/s is the default for 1.44M floppies.
'''
if rate & ~0x03:
raise ValueError('invalid data rate for floppy')
io.outb(_ccr_port, rate)
def _reg_property(offset, read=True, write=True):
'''Return a property that manipulates the register at `offset`.'''
if read: fget = lambda self: io.inb(self.io_base + offset)
else: fget = None
if write: fset = lambda self, v: io.outb(self.io_base + offset, v)
else: fset = None
return property(fget, fset)
def _program_dma(self, mode, length, dest):
io.outb(0x0a, 6)
io.outb(0x0c, 0)
io.outb(0x0b, mode)
length -= 1
io.outb(0x05, length & 0xff)
io.outb(0x05, length >> 8)
io.outb(0x81, dest >> 16)
io.outb(0x04, dest & 0xff)
io.outb(0x04, (dest >> 8) & 0xff)
io.outb(0x0a, 2)
def _write_data(self, byte):
'''Wait for FDC to become ready, then write `byte` to the data register.'''
msr = self._wait_rqm()
if msr & _msr_dio:
raise StateError('trying to write, but FDC expects a read')
io.outb(_data_port, byte)
def _reset(self):
io.outb(_dor_port, 0)
io.outb(_dor_port, _dor_not_reset)
self._set_datarate(0)
for _ in xrange(4):
self._check_interrupt_status()
def set_motor(self, state):
if state and (self.motor_on is False):
io.outb(_dor_port, _dor_not_reset | _dor_dma | _dor_mota)
self.motor_on_at = uuutime.get_time()
self.motor_on = True
def read_chunk(index):
io.outb(0x70, index)
chunk = io.inb(0x71)
print 'read %x' % chunk
return (chunk & 0xf0) * 10 + (chunk & 0x0f)