def test_block_conversion():
"""
In the current test are tested the outputs of the
converted testbench in verilog and VHDL with the outputs
of the myhdl module
"""
samples, frac_bits, nbits = 50, 14, 8
pixel_bits, num_fractional_bits = nbits, frac_bits
rgb, ycbcr = RGB(pixel_bits), YCbCr(pixel_bits)
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
in_out_data = InputsAndOutputs(samples)
in_out_data.initialize()
exp_y, exp_cb, exp_cr = in_out_data.get_rom_tables()[0]
in_r, in_g, in_b = in_out_data.get_rom_tables()[1]
y_s, cb_s, cr_s = [Signal(intbv(0)[pixel_bits:]) for _ in range(3)]
@myhdl.block
def bench_color_trans():
tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits)
tbclk = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
@instance
def tbstim():
yield reset.negedge
rgb.data_valid.next = True
for i in range(samples):
# rgb signal assignment in the dut
rgb.red.next = in_r[i]
rgb.green.next = in_g[i]
rgb.blue.next = in_b[i]
if ycbcr.data_valid == 1:
# expected_outputs signal assignment
y_s.next = exp_y[i - 3]
cb_s.next = exp_cb[i - 3]
cr_s.next = exp_cr[i - 3]
yield delay(1)
print("Expected outputs ===>Y:%d Cb:%d Cr:%d" %
(y_s, cb_s, cr_s))
print("Actual outputs ===>Y:%d Cb:%d Cr:%d" %
(ycbcr.y, ycbcr.cb, ycbcr.cr))
print("----------------------------")
yield clock.posedge
raise StopSimulation
return tbdut, tbclk, tbstim, tbrst
assert bench_color_trans().verify_convert() == 0
def convert():
ycbcr = YCbCr_v2()
rgb = RGB()
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
analyze.simulator = 'ghdl'
assert rgb2ycbcr_v2(rgb, ycbcr, clock, reset,
num_fractional_bits=14).analyze_convert() == 0
def test_color_translation_v2():
"""
In the current test are tested the outputs
of the rgb2ycbcr_v2 module with the outputs of a
python color space conversion function
"""
samples, frac_bits, nbits = 8, 14, 8
pixel_bits, num_fractional_bits = nbits, frac_bits
rgb, ycbcr = RGB(pixel_bits), YCbCr_v2(pixel_bits)
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
in_out_data = InputsAndOutputs(samples)
in_out_data.initialize()
@myhdl.block
def bench_color_trans():
tbdut = rgb2ycbcr_v2(rgb, ycbcr, clock, reset, num_fractional_bits)
tbclk = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
rgb.data_valid.next = True
for i in range(samples):
for j in range(3):
# rgb signal assignment in the dut
rgb.red.next = in_out_data.inputs['red'][i]
rgb.green.next = in_out_data.inputs['green'][i]
rgb.blue.next = in_out_data.inputs['blue'][i]
rgb.color_mode.next = j
yield clock.posedge
@instance
def monitor():
samples_count = 0
output_list = []
yield ycbcr.data_valid.posedge
yield delay(1)
while samples_count != samples:
for i in range(3):
output_list.append(int(ycbcr.data_out))
yield clock.posedge
yield delay(1)
print_results(in_out_data.expected_outputs, output_list,
samples_count)
output_list = []
samples_count += 1
raise StopSimulation
return tbdut, tbclk, tbstim, monitor
run_testbench(bench_color_trans)
def convert():
input_interface = RGB()
output_interface = outputs_frontend_new()
clock = Signal(bool(0))
reset = ResetSignal(0, active=True, async=False)
inst = frontend_top_level_v2(input_interface, output_interface, clock,
reset)
inst.convert(hdl='vhdl')
inst.convert(hdl='verilog')
def test_color_translation():
"""
In the current test are tested the outputs
of the rgb2ycbcr module with the outputs of a
python color space conversion function
"""
samples, frac_bits, nbits = 50, 14, 8
pixel_bits, num_fractional_bits = nbits, frac_bits
rgb, ycbcr = RGB(pixel_bits), YCbCr(pixel_bits)
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
in_out_data = InputsAndOutputs(samples)
in_out_data.initialize()
@myhdl.block
def bench_color_trans():
tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits)
tbclk = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
rgb.data_valid.next = True
for i in range(samples):
# rgb signal assignment in the dut
rgb.red.next = in_out_data.inputs['red'][i]
rgb.green.next = in_out_data.inputs['green'][i]
rgb.blue.next = in_out_data.inputs['blue'][i]
if ycbcr.data_valid == 1:
for ycbcr_act, val in zip(
('y', 'cb', 'cr'),
(int(ycbcr.y), int(ycbcr.cb), int(ycbcr.cr))):
in_out_data.actual_outputs[ycbcr_act].append(val)
yield clock.posedge
print_results(in_out_data.inputs, in_out_data.expected_outputs,
in_out_data.actual_outputs)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_color_trans)
def frontend_top_level_v2(inputs, outputs, clock, reset, N=8):
"""Frontend Part of the JPEG Encoder
This part combines the color space conversion, 2D-DCT and zig-zag scan modules.
It takes serially each input pixel (Red, Green, Blue) and when it computes the first block
it takes another two times the same block in order to compute the other components. First
outputs the Y block, then the Cb block and last the Cr block. The processing of this part
is continuous and it never stops.
Inputs:
red, green, blue, data_valid, clock, reset
Outputs:
data_out, data_valid
"""
"""Color Space Conversion"""
rgb2ycbcr_out = YCbCr_v2()
inputs_reg = RGB()
color_space_converter = rgb2ycbcr_v2(inputs_reg, rgb2ycbcr_out, clock,
reset)
"""2D-DCT Transformation"""
dct_2d_input = input_interface()
dct_2d_output = outputs_2d()
dct_2d_inst = dct_2d(dct_2d_input, dct_2d_output, clock, reset)
"""Zig-Zag Module"""
zig_zag_out = outputs_2d()
zig_zag_inst = zig_zag(dct_2d_output, zig_zag_out, clock, reset)
"""Intermediate signals"""
input_counter = Signal(intbv(0, min=0, max=64))
color_mode = Signal(intbv(0, min=0, max=3))
output_counter = Signal(intbv(0, min=0, max=64))
start_out = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def input_reg():
inputs_reg.red.next = inputs.red
inputs_reg.green.next = inputs.green
inputs_reg.blue.next = inputs.blue
inputs_reg.data_valid.next = inputs.data_valid
inputs_reg.color_mode.next = color_mode
@always_seq(clock.posedge, reset=reset)
def color_space_to_dct():
"""signal assignment from color_space_conversion module to dct_2d inputs"""
if rgb2ycbcr_out.data_valid:
dct_2d_input.data_in.next = rgb2ycbcr_out.data_out
dct_2d_input.data_valid.next = rgb2ycbcr_out.data_valid
@always_seq(clock.posedge, reset=reset)
def first_control_signals_update():
"""Is used to update the control signal color_mode for the first mux of the rgb2ycbcr
output to 2d dct"""
if inputs.data_valid:
if input_counter == 63:
input_counter.next = 0
if color_mode == 2:
color_mode.next = 0
else:
color_mode.next = color_mode + 1
else:
input_counter.next = input_counter + 1
@always_comb
def set_start_out():
if zig_zag_out.data_valid:
start_out.next = True
@always_seq(clock.posedge, reset=reset)
def data_valid_assign():
if zig_zag_out.data_valid:
outputs.data_valid.next = zig_zag_out.data_valid
@always_seq(clock.posedge, reset=reset)
def zig_zag_to_output_mux():
"""signal assignment from zig zag to output"""
if start_out:
outputs.data_out.next = zig_zag_out.out_sigs[output_counter]
@always_seq(clock.posedge, reset=reset)
def output_counter_reset():
if start_out:
if output_counter == 63:
output_counter.next = 0
else:
output_counter.next = output_counter + 1
return (color_space_converter, zig_zag_inst, dct_2d_inst,
color_space_to_dct, zig_zag_to_output_mux,
first_control_signals_update, set_start_out, output_counter_reset,
input_reg, data_valid_assign)
def test_color_translation_conversion_v2():
"""
In the current test are tested the outputs
of the rgb2ycbcr_v2 module with the outputs of a
python color space conversion function
"""
samples, frac_bits, nbits = 8, 14, 8
pixel_bits, num_fractional_bits = nbits, frac_bits
rgb, ycbcr = RGB(pixel_bits), YCbCr_v2(pixel_bits)
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
in_out_data = InputsAndOutputs(samples)
in_out_data.initialize()
exp_y, exp_cb, exp_cr = in_out_data.get_rom_tables()[0]
in_r, in_g, in_b = in_out_data.get_rom_tables()[1]
print_sig = Signal(intbv(0, min=0, max=2**nbits))
@myhdl.block
def bench_color_trans():
tbdut = rgb2ycbcr_v2(rgb, ycbcr, clock, reset, num_fractional_bits)
tbclk = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
@instance
def tbstim():
yield reset.negedge
rgb.data_valid.next = True
for i in range(samples):
for j in range(3):
# rgb signal assignment in the dut
rgb.red.next = in_r[i]
rgb.green.next = in_g[i]
rgb.blue.next = in_b[i]
rgb.color_mode.next = j
yield clock.posedge
@instance
def monitor():
samples_count = 0
yield ycbcr.data_valid.posedge
yield delay(1)
while samples_count != samples:
for i in range(3):
if i == 0:
print_sig.next = exp_y[samples_count]
elif i == 1:
print_sig.next = exp_cb[samples_count]
else:
print_sig.next = exp_cr[samples_count]
yield delay(1)
print("%d %d" % (ycbcr.data_out, print_sig))
yield clock.posedge
samples_count += 1
raise StopSimulation
return tbdut, tbclk, tbstim, monitor, tbrst
verify.simulator = "ghdl"
assert bench_color_trans().verify_convert() == 0