def bench_dct_1d():
tdut = dct_1d(inputs, outputs, clock, reset, fract_bits, out_prec, N)
tbclk = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in range(N):
inputs.data_in.next = in_out_data.inputs[i][j]
yield clock.posedge
@instance
def monitor():
outputs_count = 0
while(outputs_count != samples):
yield clock.posedge
yield delay(1)
if outputs.data_valid:
# convert flat signal to array of signals
out_print(in_out_data.outputs[outputs_count],
outputs.out_sigs)
outputs_count += 1
raise StopSimulation
return tdut, tbclk, tbstim, monitor
def bench_dct_1d():
print_sig = [Signal(intbv(0, min=-2**out_prec, max=2**out_prec))
for _ in range(N)]
print_sig_1 = [Signal(intbv(0, min=-2**out_prec, max=2**out_prec))
for _ in range(N)]
tdut = dct_1d(inputs, outputs, clock, reset, fract_bits, out_prec, N)
tbclk = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
@instance
def tbstim():
yield reset.negedge
inputs.data_valid.next =True
for i in range(samples * N):
inputs.data_in.next = inputs_rom[i]
yield clock.posedge
print_assign = assign_array(print_sig_1, outputs.out_sigs)
@instance
def monitor():
outputs_count = 0
while outputs_count != samples:
yield clock.posedge
yield delay(1)
if outputs.data_valid:
for i in range(N):
print_sig[i].next = expected_outputs_rom[outputs_count * 8 + i]
yield delay(1)
print("Expected Outputs")
for i in range(N):
print("%d" % print_sig[i])
print("Actual Outputs")
for i in range(N):
print("%d" % print_sig_1[i])
print("------------------------")
outputs_count += 1
raise StopSimulation
return tdut, tbclk, tbstim, monitor, tbrst, print_assign
