def tbstim():
"""we send test cases here"""
# reset the block before processing
yield pulse_reset(reset, clock)
# select Cb or Cr component
color = component.y2_space
# process Cb or Cr component
yield quant_top_block_process(clock, quant_ctrl, color,
quanto_datastream, quanti_datastream,
quant_in, quant_rom, max_addr, 1)
print("===============================================")
# select Y1 or Y2 component
color = component.cr_space
# process Cb or Cr component
yield quant_top_block_process(clock, quant_ctrl, color,
quanto_datastream, quanti_datastream,
quant_in, quant_rom, max_addr, 1)
raise StopSimulation
def tbstim():
"""We send the inputs from here"""
# reset the module before sending inputs
yield pulse_reset(reset, clock)
# select Cb or Cr component
color = component.y2_space
# process the component selected
yield quant_block_process(
clock, color_component, color, quant_in, quant_rom,
quant_input_stream, quant_output_stream, max_addr)
yield clock.posedge
print ("====================================")
# select Y1 or Y2 component
color = component.cb_space
# process the component selected
yield quant_block_process(
clock, color_component, color, quant_in, quant_rom,
quant_input_stream, quant_output_stream, max_addr)
yield clock.posedge
raise StopSimulation
def tbstim():
"""We send the inputs from here"""
# reset the module before sending inputs
yield pulse_reset(reset, clock)
# select Cb or Cr component
color = component.y2_space
# process the component selected
yield quant_block_process(clock, color_component, color, quant_in,
quant_rom, quant_input_stream,
quant_output_stream, max_addr)
yield clock.posedge
print("====================================")
# select Y1 or Y2 component
color = component.cb_space
# process the component selected
yield quant_block_process(clock, color_component, color, quant_in,
quant_rom, quant_input_stream,
quant_output_stream, max_addr)
yield clock.posedge
raise StopSimulation
def tbstim():
"""we send test cases here"""
# reset the block before processing
yield pulse_reset(reset, clock)
# select Cb or Cr component
color = component.y2_space
# process Cb or Cr component
yield quant_top_block_process(
clock, quant_ctrl, color, quanto_datastream,
quanti_datastream, quant_in, quant_rom, max_addr, 1)
print ("===============================================")
# select Y1 or Y2 component
color = component.cr_space
# process Cb or Cr component
yield quant_top_block_process(
clock, quant_ctrl, color, quanto_datastream,
quanti_datastream, quant_in, quant_rom, max_addr, 1)
raise StopSimulation
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in range(N):
inputs.data_in.next = in_out_data.inputs[i][j]
yield clock.posedge
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in range(N**2):
inputs.out_sigs[j].next = in_out_data.inputs[i][j]
yield clock.posedge
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in in_out_data.inputs[i]:
for k in j:
inputs.data_in.next = k
yield clock.posedge
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for n in range(3):
for j in range(N):
for k in range(N):
inputs.red.next = in_out_data.inputs[i][0][j][k]
inputs.green.next = in_out_data.inputs[i][1][j][k]
inputs.blue.next = in_out_data.inputs[i][2][j][k]
yield clock.posedge
def tbstim():
yield pulse_reset(reset, clock)
rgb.data_valid.next = True
for i in range(samples):
for j in range(3):
# rgb signal assignment in the dut
rgb.red.next = in_out_data.inputs['red'][i]
rgb.green.next = in_out_data.inputs['green'][i]
rgb.blue.next = in_out_data.inputs['blue'][i]
rgb.color_mode.next = j
yield clock.posedge
def tbstim():
"""Huffman input tests given here"""
# reset the stimulus before sending data in
yield pulse_reset(reset, clock)
bufferdatabus.buffer_sel.next = False
# send y1 component into the module
color = component.y1_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_y, runlength_test_y,
vli_size_test_y, clock)
print ("=======================================")
# read y1 component from the double FIFO
bufferdatabus.buffer_sel.next = True
yield read_block(bufferdatabus, clock)
print ("==============================")
# send cb component into the module
color = component.cb_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_cb, runlength_test_cb,
vli_size_test_cb, clock)
print ("==========================================")
# read cb component from the double FIFO
bufferdatabus.buffer_sel.next = False
yield clock.posedge
yield read_block(bufferdatabus, clock)
print ("==============================")
# send cr component into the module
color = component.cr_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_cr, runlength_test_cr,
vli_size_test_cr, clock)
print ("============================")
# read cr component from the double FIFO
bufferdatabus.buffer_sel.next = True
yield clock.posedge
yield read_block(bufferdatabus, clock)
print ("==============================")
yield toggle_signal(huffmancntrl.sof, clock)
raise StopSimulation
def tbstim():
"""Huffman input tests given here"""
# reset the stimulus before sending data in
yield pulse_reset(reset, clock)
bufferdatabus.buffer_sel.next = False
# send y1 component into the module
color = component.y1_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_y, runlength_test_y,
vli_size_test_y, clock)
print("=======================================")
# read y1 component from the double FIFO
bufferdatabus.buffer_sel.next = True
yield read_block(bufferdatabus, clock)
print("==============================")
# send cb component into the module
color = component.cb_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_cb, runlength_test_cb,
vli_size_test_cb, clock)
print("==========================================")
# read cb component from the double FIFO
bufferdatabus.buffer_sel.next = False
yield clock.posedge
yield read_block(bufferdatabus, clock)
print("==============================")
# send cr component into the module
color = component.cr_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_cr, runlength_test_cr,
vli_size_test_cr, clock)
print("============================")
# read cr component from the double FIFO
bufferdatabus.buffer_sel.next = True
yield clock.posedge
yield read_block(bufferdatabus, clock)
print("==============================")
yield toggle_signal(huffmancntrl.sof, clock)
raise StopSimulation
def tbstim():
"""stimulus generates inputs for entropy coder"""
yield pulse_reset(reset, clock)
for i in range(-2**(width-1), 2**(width-1), 1):
data_in.next = i
yield clock.posedge
yield clock.posedge
amplitude_ref, size_ref = entropy_encode(int(data_in))
# comparing with the data present in reference
assert size == size_ref
assert amplitude == amplitude_ref
raise StopSimulation
def tbstim():
"""stimulus generates inputs for entropy coder"""
# reset the module
yield pulse_reset(reset, clock)
# send input test cases into the module
for i in range(-2**(width_data-1)+1, 2**(width_data-1), 1):
data_in.next = i
yield clock.posedge
yield clock.posedge
# extract results from reference design
amplitude_ref, size_ref = entropy_encode(int(data_in))
# comparing reference and module results
assert size == size_ref
assert amplitude == amplitude_ref
raise StopSimulation
def tbstim():
"""stimulus generates inputs for entropy coder"""
# reset the module
yield pulse_reset(reset, clock)
# send input test cases into the module
for i in range(-2 ** (width_data - 1) + 1, 2 ** (width_data - 1), 1):
data_in.next = i
yield clock.posedge
yield clock.posedge
# extract results from reference design
amplitude_ref, size_ref = entropy_encode(int(data_in))
# comparing reference and module results
assert size == size_ref
assert amplitude == amplitude_ref
raise StopSimulation
def tbstim():
"""Test cases are given here"""
# reset signal
yield pulse_reset(reset, clock)
list_output = []
list_output_ref = []
# all the possible tests from -2048 to 2048 given here
for dividend_temp in range(-2**(width_data), 2**(width_data), 1):
for divisor_temp in range(0, 256, 1):
dividend.next = dividend_temp
divisor.next = divisor_temp
result = divider_ref(dividend_temp, divisor_temp)
list_output_ref.append(result)
yield clock.posedge
list_output.append(int(quotient))
yield clock.posedge
list_output.append(int(quotient))
yield clock.posedge
list_output.append(int(quotient))
yield clock.posedge
list_output.append(int(quotient))
yield clock.posedge
list_output.append(int(quotient))
# pop the zeroes stored in the list because of pipelining
list_output.pop(0)
list_output.pop(0)
list_output.pop(0)
list_output.pop(0)
# compare reference design divider output with that of HDL divider
for item1, item2 in zip(list_output, list_output_ref):
print("quotient %d quotient_ref %d" % (item1, item2))
assert item1 == item2
raise StopSimulation
def tbstim():
"""Test cases are given here"""
# reset signal
yield pulse_reset(reset, clock)
list_output = []
list_output_ref = []
# all the possible tests from -2048 to 2048 given here
for dividend_temp in range(-2**(width_data), 2**(width_data), 1):
for divisor_temp in range(0, 256, 1):
dividend.next = dividend_temp
divisor.next = divisor_temp
result = divider_ref(dividend_temp, divisor_temp)
list_output_ref.append(result)
yield clock.posedge
list_output.append(int(quotient))
yield clock.posedge
list_output.append(int(quotient))
yield clock.posedge
list_output.append(int(quotient))
yield clock.posedge
list_output.append(int(quotient))
yield clock.posedge
list_output.append(int(quotient))
# pop the zeroes stored in the list because of pipelining
list_output.pop(0)
list_output.pop(0)
list_output.pop(0)
list_output.pop(0)
# compare reference design divider output with that of HDL divider
for item1, item2 in zip(list_output, list_output_ref):
print ("quotient %d quotient_ref %d" % (item1, item2))
assert item1 == item2
raise StopSimulation
def tbstim():
"""stimulus generates inputs for byte stuffer"""
# reset the module
yield pulse_reset(reset, clock)
yield toggle_signal(bs_cntrl.start, clock)
yield clock.posedge
# send input data
for i in range(64):
# send 0xFF bytes
if i % 5 == 0:
bs_in_stream.data_in.next = 0xFF
# send other bytes
else:
bs_in_stream.data_in.next = i
yield clock.posedge
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
# assert fifo empty when all the inputs are over
if i == 63:
bs_in_stream.fifo_empty.next = True
for _ in range(3):
yield clock.posedge
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
yield toggle_signal(bs_cntrl.sof, clock)
# if last byte is 0xFF. Print the zero's stuffed
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
print("total encoded bytes is %d" % num_enc_bytes)
raise StopSimulation
def tbstim():
"""stimulus generates inputs for byte stuffer"""
# reset the module
yield pulse_reset(reset, clock)
yield toggle_signal(bs_cntrl.start, clock)
yield clock.posedge
# send input data
for i in range(64):
# send 0xFF bytes
if i % 5 == 0:
bs_in_stream.data_in.next = 0xFF
# send other bytes
else:
bs_in_stream.data_in.next = i
yield clock.posedge
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
# assert fifo empty when all the inputs are over
if i == 63:
bs_in_stream.fifo_empty.next = True
for _ in range(3):
yield clock.posedge
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
yield toggle_signal(bs_cntrl.sof, clock)
# if last byte is 0xFF. Print the zero's stuffed
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
print("total encoded bytes is %d" % num_enc_bytes)
raise StopSimulation
def tbstim():
yield pulse_reset(reset, clock)
rgb.data_valid.next = True
for i in range(samples):
# rgb signal assignment in the dut
rgb.red.next = in_out_data.inputs['red'][i]
rgb.green.next = in_out_data.inputs['green'][i]
rgb.blue.next = in_out_data.inputs['blue'][i]
if ycbcr.data_valid == 1:
for ycbcr_act, val in zip(
('y', 'cb', 'cr'),
(int(ycbcr.y), int(ycbcr.cb), int(ycbcr.cr))):
in_out_data.actual_outputs[ycbcr_act].append(val)
yield clock.posedge
print_results(in_out_data.inputs, in_out_data.expected_outputs,
in_out_data.actual_outputs)
raise StopSimulation
def tbstim():
yield pulse_reset(reset, clock)
rgb.data_valid.next = True
for i in range(samples):
# rgb signal assignment in the dut
rgb.red.next = in_out_data.inputs['red'][i]
rgb.green.next = in_out_data.inputs['green'][i]
rgb.blue.next = in_out_data.inputs['blue'][i]
if ycbcr.data_valid == 1:
for ycbcr_act, val in zip(('y', 'cb', 'cr'),
(int(ycbcr.y), int(ycbcr.cb),
int(ycbcr.cr))):
in_out_data.actual_outputs[ycbcr_act].append(val)
yield clock.posedge
print_results(in_out_data.inputs, in_out_data.expected_outputs,
in_out_data.actual_outputs)
raise StopSimulation
def tbstim():
"""Test inputs given here"""
# reset before sending data
yield pulse_reset(reset, clock)
# components of type y1 or y2 processed
yield block_process(
clock, red_pixels_1,
datastream,
rlesymbols,
rleconfig, component.y1_space, max_count=max_addr_cnt
)
print ("======================")
# components of type y1 or y2 processed
yield block_process(
clock, red_pixels_2,
datastream,
rlesymbols,
rleconfig, component.y2_space, max_count=max_addr_cnt
)
print ("=====================")
# components of type cb processes
yield block_process(
clock, green_pixels_1,
datastream,
rlesymbols,
rleconfig, component.cb_space, max_count=max_addr_cnt
)
print ("=====================")
# components od type cb processed
yield block_process(
clock, green_pixels_2,
datastream,
rlesymbols,
rleconfig, component.cb_space, max_count=max_addr_cnt
)
print ("=====================")
# components of type cr processed
yield block_process(
clock, blue_pixels_1,
datastream,
rlesymbols,
rleconfig, component.cr_space, max_count=max_addr_cnt
)
print ("=====================")
# components of type cr processed
yield block_process(
clock, blue_pixels_2,
datastream,
rlesymbols,
rleconfig, component.cr_space, max_count=max_addr_cnt
)
print ("=====================")
# start of new frame asserts
rleconfig.sof.next = True
yield clock.posedge
raise StopSimulation
def tbstim():
"""write data inputs to double buffer"""
print("start simulation")
# disable read and write
dfifo_bus.write.next = False
dfifo_bus.read.next = False
# reset before sending data
yield pulse_reset(reset, clock)
# check if FIFO is empty
assert dfifo_bus.empty
# select first buffer
buffer_sel.next = False
yield clock.posedge
# write first data into double buffer
dfifo_bus.write.next = True
# convert signed number to unsigned
dfifo_bus.write_data.next = -1 and 0xFF
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
# write data into double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0xA1
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
# write data into rle double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0x11
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# write data into rle double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0x101
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# write data into rle double buffer
for test_cases in range(64):
if test_cases < 28:
buffer_sel.next = False
yield clock.posedge
else:
buffer_sel.next = True
yield clock.posedge
dfifo_bus.write.next = True
dfifo_bus.write_data.next = test_cases
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
print("printing second FIFO outputs")
# read data
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print("%d" % dfifo_bus.read_data)
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print("%d" % dfifo_bus.read_data)
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print("%d" % dfifo_bus.read_data)
for _ in range(29):
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print("%d" % dfifo_bus.read_data)
buffer_sel.next = False
yield clock.posedge
print("printing first FIFO outputs")
# read some more data
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print("%d" % dfifo_bus.read_data)
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print("%d" % dfifo_bus.read_data)
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print("%d" % dfifo_bus.read_data)
for _ in range(33):
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print("%d" % dfifo_bus.read_data)
raise StopSimulation
def tbstim():
"""stimulus generates inputs for entropy coder"""
# reset the module
output_model = [0] * 64
yield pulse_reset(reset, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
write_addr.next = 64
for i in range(64):
data_in.next = i % 25
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
for _ in range(35):
yield clock.posedge
# start the blocks
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 16
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 47
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 28
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 40
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 31
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
print("===================")
for i in range(addr):
print("outputs_hdl %d" % output_model[i])
print("======================")
# get outputs from reference values
output_ref = []
output_ref = backend_soft()
for i in range(len(output_ref)):
print("outputs_soft %d" % int(output_ref[i], 2))
print("===========================")
# compare reference and HDL outputs
for i in range(len(output_ref)):
assert int(output_ref[i], 2) == output_model[i]
raise StopSimulation
def tbstim():
"""Test inputs given here"""
# reset before sending data
yield pulse_reset(reset, clock)
# components of type y1 or y2 processed
yield block_process(
clock, red_pixels_1,
datastream,
rlesymbols,
rleconfig, component.y1_space, max_count=max_addr_cnt
)
print ("======================")
# components of type y1 or y2 processed
yield block_process(
clock, red_pixels_2,
datastream,
rlesymbols,
rleconfig, component.y2_space, max_count=max_addr_cnt
)
print ("=====================")
# components of type cb processes
yield block_process(
clock, green_pixels_1,
datastream,
rlesymbols,
rleconfig, component.cb_space, max_count=max_addr_cnt
)
print ("=====================")
# components od type cb processed
yield block_process(
clock, green_pixels_2,
datastream,
rlesymbols,
rleconfig, component.cb_space, max_count=max_addr_cnt
)
print ("=====================")
# components of type cr processed
yield block_process(
clock, blue_pixels_1,
datastream,
rlesymbols,
rleconfig, component.cr_space, max_count=max_addr_cnt
)
print ("=====================")
# components of type cr processed
yield block_process(
clock, blue_pixels_2,
datastream,
rlesymbols,
rleconfig, component.cr_space, max_count=max_addr_cnt
)
print ("=====================")
# start of new frame asserts
rleconfig.sof.next = True
yield clock.posedge
raise StopSimulation
def tbstim():
"""RLE input tests given here"""
# reset the stimulus before sending data in
yield pulse_reset(reset, clock)
# write y1 component into 1st buffer
bufferdatabus.buffer_sel.next = False
yield clock.posedge
yield write_block(
clock, red_pixels_1,
datastream,
rleconfig, component.y1_space
)
yield clock.posedge
print ("============================")
# read y1 component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write y2 component into 2nd Buffer
yield write_block(
clock, red_pixels_2,
datastream,
rleconfig, component.y2_space
)
yield clock.posedge
print ("============================")
# read y2 component from 2nd Buffer
yield read_block(False, bufferdatabus, clock)
# write cb Component into 1st Buffer
yield write_block(
clock, green_pixels_1,
datastream,
rleconfig, component.cb_space
)
yield clock.posedge
print ("=============================")
# read cb component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write cb Component into 2nd Buffer
yield write_block(
clock, green_pixels_2,
datastream,
rleconfig, component.cb_space
)
yield clock.posedge
print ("==============================")
# read cb component from 2nd Buffer
yield read_block(False, bufferdatabus, clock)
# write cr Component into 1st Buffer
yield write_block(
clock, blue_pixels_1,
datastream,
rleconfig, component.cr_space
)
yield clock.posedge
print ("==============================")
# read cr component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write cr Component into 2nd Buffer
yield write_block(
clock, blue_pixels_2,
datastream,
rleconfig, component.cr_space
)
yield clock.posedge
print ("==============================")
# read cr component from 1st Buffer
yield read_block(False, bufferdatabus, clock)
print ("==============================")
# end of stream when sof asserts
yield clock.posedge
rleconfig.sof.next = True
yield clock.posedge
raise StopSimulation
def tbstim():
"""stimulus generates inputs for entropy coder"""
# reset the module
output_model = [0]*64
yield pulse_reset(reset, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
write_addr.next = 64
for i in range(64):
data_in.next = i % 25
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
for _ in range(35):
yield clock.posedge
# start the blocks
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 16
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 47
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 28
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 40
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 31
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
print ("===================")
for i in range(addr):
print ("outputs_hdl %d" % output_model[i])
print ("======================")
# get outputs from reference values
output_ref = []
output_ref = backend_soft()
for i in range(len(output_ref)):
print ("outputs_soft %d" % int(output_ref[i], 2))
print ("===========================")
# compare reference and HDL outputs
for i in range(len(output_ref)):
assert int(output_ref[i], 2) == output_model[i]
raise StopSimulation
def tbstim():
"""RLE input tests given here"""
# reset the stimulus before sending data in
yield pulse_reset(reset, clock)
# write y1 component into 1st buffer
bufferdatabus.buffer_sel.next = False
yield clock.posedge
yield write_block(
clock, red_pixels_1,
datastream,
rleconfig, component.y1_space
)
yield clock.posedge
print ("============================")
# read y1 component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write y2 component into 2nd Buffer
yield write_block(
clock, red_pixels_2,
datastream,
rleconfig, component.y2_space
)
yield clock.posedge
print ("============================")
# read y2 component from 2nd Buffer
yield read_block(False, bufferdatabus, clock)
# write cb Component into 1st Buffer
yield write_block(
clock, green_pixels_1,
datastream,
rleconfig, component.cb_space
)
yield clock.posedge
print ("=============================")
# read cb component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write cb Component into 2nd Buffer
yield write_block(
clock, green_pixels_2,
datastream,
rleconfig, component.cb_space
)
yield clock.posedge
print ("==============================")
# read cb component from 2nd Buffer
yield read_block(False, bufferdatabus, clock)
# write cr Component into 1st Buffer
yield write_block(
clock, blue_pixels_1,
datastream,
rleconfig, component.cr_space
)
yield clock.posedge
print ("==============================")
# read cr component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write cr Component into 2nd Buffer
yield write_block(
clock, blue_pixels_2,
datastream,
rleconfig, component.cr_space
)
yield clock.posedge
print ("==============================")
# read cr component from 1st Buffer
yield read_block(False, bufferdatabus, clock)
print ("==============================")
# end of stream when sof asserts
yield clock.posedge
rleconfig.sof.next = True
yield clock.posedge
raise StopSimulation
def tbstim():
# reset the stimulus before sending data in
yield pulse_reset(reset, clock)
# write Y1 component into 1st buffer
bufferdatabus.buffer_sel.next = False
yield clock.posedge
yield write_block(
clock, red_pixels_1,
indatastream,
rleconfig, pixel.Y1
)
yield clock.posedge
print("============================")
# read Y1 component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write Y2 component into 2nd Buffer
yield write_block(
clock, red_pixels_2,
indatastream,
rleconfig, pixel.Y2
)
yield clock.posedge
print("============================")
# read Y2 component from 2nd Buffer
yield read_block(False, bufferdatabus, clock)
# write Cb Component into 1st Buffer
yield write_block(
clock, green_pixels_1,
indatastream,
rleconfig, pixel.Cb
)
yield clock.posedge
print("=============================")
# read Cb component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write Cb Component into 2nd Buffer
yield write_block(
clock, green_pixels_2,
indatastream,
rleconfig, pixel.Cb
)
yield clock.posedge
print("==============================")
# read Cb component from 2nd Buffer
yield read_block(False, bufferdatabus, clock)
# write Cr Component into 1st Buffer
yield write_block(
clock, blue_pixels_1,
indatastream,
rleconfig, pixel.Cr
)
yield clock.posedge
print("==============================")
# read Cr component from 1st Buffer
yield read_block(True, bufferdatabus, clock)
# write Cr Component into 2nd Buffer
yield write_block(
clock, blue_pixels_2,
indatastream,
rleconfig, pixel.Cr
)
yield clock.posedge
print("==============================")
# read Cr component from 1st Buffer
yield read_block(False, bufferdatabus, clock)
print("==============================")
# end of stream when sof asserts
yield clock.posedge
rleconfig.sof.next = True
yield clock.posedge
raise StopSimulation
def tbstim():
"""write data inputs to double buffer"""
print("start simulation")
# disable read and write
dfifo_bus.write.next = False
dfifo_bus.read.next = False
# reset before sending data
yield pulse_reset(reset, clock)
# check if FIFO is empty
assert dfifo_bus.empty
# select first buffer
buffer_sel.next = False
yield clock.posedge
# write first data into double buffer
dfifo_bus.write.next = True
# convert signed number to unsigned
dfifo_bus.write_data.next = -1 and 0xFF
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
# write data into double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0xA1
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
# write data into rle double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0x11
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# write data into rle double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0x101
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# write data into rle double buffer
for test_cases in range(64):
if test_cases < 28:
buffer_sel.next = False
yield clock.posedge
else:
buffer_sel.next = True
yield clock.posedge
dfifo_bus.write.next = True
dfifo_bus.write_data.next = test_cases
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data and -1 == -1
dfifo_bus.read.next = False
buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data == 0xA1
dfifo_bus.read.next = False
buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data == 0x11
dfifo_bus.read.next = False
buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data == 0x101
dfifo_bus.read.next = False
# read data from rle double buffer
for test_cases in range(64):
if test_cases < 28:
buffer_sel.next = True
yield clock.posedge
else:
buffer_sel.next = False
yield clock.posedge
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data == test_cases
dfifo_bus.read.next = False
yield clock.posedge
assert dfifo_bus.empty
raise StopSimulation
def tbstim():
"""write data inputs to double buffer"""
print("start simulation")
# disable read and write
dfifo_bus.write_enable.next = False
dfifo_bus.read_req.next = False
# reset before sending data
yield pulse_reset(reset, clock)
assert dfifo_bus.fifo_empty
# select first buffer
dfifo_bus.buffer_sel.next = False
yield clock.posedge
# write first data into rle double buffer
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = -1 and 0xFF
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
assert dfifo_bus.fifo_empty
# write data into rle double buffer
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = 0xA1
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
assert dfifo_bus.fifo_empty
# write data into rle double buffer
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = 0x11
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
# write data into rle double buffer
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = 0x101
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
# write data into rle double buffer
for test_cases in range(64):
if test_cases < 28:
dfifo_bus.buffer_sel.next = False
yield clock.posedge
else:
dfifo_bus.buffer_sel.next = True
yield clock.posedge
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = test_cases
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out and -1 == -1
dfifo_bus.read_req.next = False
dfifo_bus.buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out == 0xA1
dfifo_bus.read_req.next = False
dfifo_bus.buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out == 0x11
dfifo_bus.read_req.next = False
dfifo_bus.buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out == 0x101
dfifo_bus.read_req.next = False
# read data from rle double buffer
for test_cases in range(64):
if test_cases < 28:
dfifo_bus.buffer_sel.next = True
yield clock.posedge
else:
dfifo_bus.buffer_sel.next = False
yield clock.posedge
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out == test_cases
dfifo_bus.read_req.next = False
yield clock.posedge
assert dfifo_bus.fifo_empty
raise StopSimulation
def tbstim():
"""write data inputs to double buffer"""
print("start simulation")
# disable read and write
dfifo_bus.write.next = False
dfifo_bus.read.next = False
# reset before sending data
yield pulse_reset(reset, clock)
# check if FIFO is empty
assert dfifo_bus.empty
# select first buffer
buffer_sel.next = False
yield clock.posedge
# write first data into double buffer
dfifo_bus.write.next = True
# convert signed number to unsigned
dfifo_bus.write_data.next = -1 and 0xFF
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
# write data into double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0xA1
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
# write data into rle double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0x11
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# write data into rle double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0x101
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# write data into rle double buffer
for test_cases in range(64):
if test_cases < 28:
buffer_sel.next = False
yield clock.posedge
else:
buffer_sel.next = True
yield clock.posedge
dfifo_bus.write.next = True
dfifo_bus.write_data.next = test_cases
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
print ("printing second FIFO outputs")
# read data
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print ("%d" % dfifo_bus.read_data)
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print ("%d" % dfifo_bus.read_data)
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print ("%d" % dfifo_bus.read_data)
for _ in range(29):
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print ("%d" % dfifo_bus.read_data)
buffer_sel.next = False
yield clock.posedge
print ("printing first FIFO outputs")
# read some more data
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print ("%d" % dfifo_bus.read_data)
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print ("%d" % dfifo_bus.read_data)
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print ("%d" % dfifo_bus.read_data)
for _ in range(33):
dfifo_bus.read.next = True
yield clock.posedge
dfifo_bus.read.next = False
yield clock.posedge
print ("%d" % dfifo_bus.read_data)
raise StopSimulation
