return "CLOCK"
else:
return "clock"
if __name__ == '__main__':
# 実際に動かす
os.chdir('.temp') # よくわからないファイルが出るので作業ディレクトリの変更
target = 'b05'
try:
os.mkdir(target)
except:
pass;
# vgファイルから組み合わせ回路を抜き出し，vgファイルに戻す
Verilog.convert_verilog_to_json(target + '.vg', output_f= target + '.json')
Verilog.extract_comb_circuit_from_verilog_json(target + '.json', target + '.json')
Verilog.convert_json_to_verilog(target + '.json', output_f=target + '_comb.vg')
# Test Pattern の 生成
settings = dict(nangate_db = '../data/Nangate/nangate45nm.db',
nangate_v = '../data/Nangate/nangate.v',
name = target,
clock = clock_judge(target),
vg = target + '_comb.vg',
stil = target + '_base.stil',
pi_constraints = '',
fault_sentence = 'add_faults -all'
)
# テストパターン生成の実行
Synopsys.system(shell='tmax', script='../template/GeneratePatternForCombination', context=settings)
settings_path()
settings = dict(nangate_db = '../data/Nangate/nangate45nm.db',
nangate_v = '../data/Nangate/nangate.v',
name = target,
clock = clock_judge(target),
vhd = '../data/ITC99/' + target + '.vhd',
vg = target + '.vg',
spf = target + '.spf',
stil = target + '.stil',
slk = target + '.slk',
stilcsv = target + '.stilcsv',
vcd = target + '.vcd',
fault = target + '_report_faults.txt',
power = target + '_report_power',
first_p = 1,
last_p = 1
)
# 論理合成をしてSDQLをもとめる
Synopsys.system(shell='dc', script='../template/LogicSynthesis', context=settings)
Synopsys.system(shell='pt', script='../template/AnalysisPass', context=settings)
Synopsys.system(shell='tmax', script='../template/GeneratePatternForSDQLwithX', context=settings)
Synopsys.system(shell='tmax', script='../template/RequestSDQL', context=settings)
# 電力をもとめる
#Synopsys.add_dump_code_in_stildpv(circuit='b05')
#Synopsys.compute_test_power(context=settings,stil_f=settings["stil"])
#Synopsys.compute_test_power(context=settings,stil_f='stil_c')
if __name__ == '__main__':
target = 'b05'
os.chdir('.temp') # よくわからないファイルが出るので作業ディレクトリの変更
settings_path()
settings = dict(nangate_db = '../data/Nangate/nangate45nm.db',
nangate_v = '../data/Nangate/nangate.v',
name = target,
clock = clock_judge(target),
vhd = '../data/ITC99/' + target + '.vhd',
vg = target + '.vg',
spf = target + '.spf',
stil = target + '.stil',
slk = target + '.slk',
stilcsv = target + '.stilcsv',
vcd = target + '.vcd',
fault = target + '_report_faults.txt',
power = target + '_report_power',
first_p = 1,
last_p = 1
)
settings['stil'] = target + '.proposexoptimise.stil'
num = SortMinTransition.pattern_num(settings['stil'])
for i in range(num):
settings['last_p'] = i + 1
os.system('echo ' + str(settings['last_p']) + ' >> ' + settings['stil'] + '.sdql')
Synopsys.system(shell='tmax', script='../template/RequestSDQL_with_p', context=settings)
