def generate_sdram_phy_py_header(self, output_file): os.makedirs(os.path.dirname(output_file), exist_ok=True) f = open(output_file, "w") f.write( get_sdram_phy_py_header(self.sdram.controller.settings.phy, self.sdram.controller.settings.timing)) f.close()
def test_ddr4(self): from litex.boards.targets.kcu105 import BaseSoC soc = BaseSoC(max_sdram_size=0x4000000) c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True) self.assertEqual(compare_with_reference(py_header, "ddr4_init.py"), True)
def test_sdr(self): from litex.boards.targets.minispartan6 import BaseSoC soc = BaseSoC() c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True) self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True)
def generate_sdram_phy_py_header(self): f = open("sdram_init.py", "w") f.write( get_sdram_phy_py_header( self.sdram.controller.settings.phy, self.sdram.controller.settings.timing ) ) f.close()
def test_ddr3(self): from litex_boards.targets.kc705 import BaseSoC soc = BaseSoC() c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header( soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) compare_with_reference(self, c_header, "ddr3_init.h") compare_with_reference(self, py_header, "ddr3_init.py")
def test_ddr4(self): from litex_boards.targets.kcu105 import BaseSoC soc = BaseSoC(max_sdram_size=0x4000000) c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header( soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) #update_c_reference(c_header, "ddr4_init.h") compare_with_reference(self, c_header, "ddr4_init.h") compare_with_reference(self, py_header, "ddr4_init.py")
def test_sdr(self): from litex_boards.targets.minispartan6 import BaseSoC soc = BaseSoC() c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header( soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) #update_c_reference(c_header, "sdr_init.h") compare_with_reference(self, c_header, "sdr_init.h") compare_with_reference(self, py_header, "sdr_init.py")
def generate_sdram_phy_py_header(self, output_file): f = open(output_file, "w") f.write( get_sdram_phy_py_header(self.sdram.controller.settings.phy, self.sdram.controller.settings.timing)) f.close()