def __init__(self, addressbits, bankbits, nranks, databits, nphases=1):
inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
self._control = CSRStorage(fields=[
CSRField("sel", size=1, values=[
("``0b0``", "Software (CPU) control."),
("``0b1`", "Hardware control (default)."),
], reset=0b0), # Defaults to HW control.
CSRField("cke", size=1),
CSRField("odt", size=1),
CSRField("reset_n", size=1),
])
for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
# # #
self.comb += If(self._control.fields.sel,
self.slave.connect(self.master)
).Else(
inti.connect(self.master)
)
for i in range(nranks):
self.comb += [phase.cke[i].eq(self._control.fields.cke) for phase in inti.phases]
self.comb += [phase.odt[i].eq(self._control.fields.odt) for phase in inti.phases if hasattr(phase, "odt")]
self.comb += [phase.reset_n.eq(self._control.fields.reset_n) for phase in inti.phases if hasattr(phase, "reset_n")]
def __init__(self, addressbits, bankbits, nranks, databits, nphases=1):
inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
self.slave = dfi.Interface(addressbits, bankbits, nranks, databits,
nphases)
self.master = dfi.Interface(addressbits, bankbits, nranks, databits,
nphases)
self._control = CSRStorage(4) # sel, cke, odt, reset_n
for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
# # #
self.comb += If(self._control.storage[0],
self.slave.connect(self.master)).Else(
inti.connect(self.master))
for i in range(nranks):
self.comb += [
phase.cke[i].eq(self._control.storage[1])
for phase in inti.phases
]
self.comb += [
phase.odt[i].eq(self._control.storage[2])
for phase in inti.phases if hasattr(phase, "odt")
]
self.comb += [
phase.reset_n.eq(self._control.storage[3]) for phase in inti.phases
if hasattr(phase, "reset_n")
]
def __init__(self,
phy_settings,
geom_settings,
timing_settings,
clk_freq,
controller_settings=ControllerSettings()):
if phy_settings.memtype == "SDR":
burst_length = phy_settings.nphases
else:
burst_length = burst_lengths[phy_settings.memtype]
address_align = log2_int(burst_length)
# Settings ---------------------------------------------------------------------------------
self.settings = controller_settings
self.settings.phy = phy_settings
self.settings.geom = geom_settings
self.settings.timing = timing_settings
nranks = phy_settings.nranks
nbanks = 2**geom_settings.bankbits
# LiteDRAM Interface (User) ----------------------------------------------------------------
self.interface = interface = LiteDRAMInterface(address_align,
self.settings)
# DFI Interface (Memory) -------------------------------------------------------------------
self.dfi = dfi.Interface(addressbits=geom_settings.addressbits,
bankbits=geom_settings.bankbits,
nranks=phy_settings.nranks,
databits=phy_settings.dfi_databits,
nphases=phy_settings.nphases)
# # #
# Refresher --------------------------------------------------------------------------------
self.submodules.refresher = self.settings.refresh_cls(
self.settings,
clk_freq=clk_freq,
zqcs_freq=self.settings.refresh_zqcs_freq,
postponing=self.settings.refresh_postponing)
# Bank Machines ----------------------------------------------------------------------------
bank_machines = []
for n in range(nranks * nbanks):
bank_machine = BankMachine(n,
address_width=interface.address_width,
address_align=address_align,
nranks=nranks,
settings=self.settings)
bank_machines.append(bank_machine)
self.submodules += bank_machine
self.comb += getattr(interface,
"bank" + str(n)).connect(bank_machine.req)
# Multiplexer ------------------------------------------------------------------------------
self.submodules.multiplexer = Multiplexer(settings=self.settings,
bank_machines=bank_machines,
refresher=self.refresher,
dfi=self.dfi,
interface=interface)
def __init__(self, addressbits, bankbits, nranks, databits, nphases=1):
inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
self.slave = dfi.Interface(addressbits, bankbits, nranks, databits,
nphases)
self.master = dfi.Interface(addressbits, bankbits, nranks, databits,
nphases)
# interface for ComputeDRAM to issue command sequence
self.cmds = dfi.Interface(addressbits, bankbits, nranks, databits,
nphases)
self.cmd_valid = Signal()
# print("Hi I'm Here")
self._control = CSRStorage(4) # sel, cke, odt, reset_n
for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
# # #
self.comb += If(~self._control.storage[0],
inti.connect(self.master)).Elif(
self.cmd_valid,
self.cmds.connect(self.master)).Else(
self.slave.connect(self.master))
'''self.comb += If(self.cmd_valid,
self.cmds.connect(self.master)
).Else(
self.slave.connect(self.master)
)'''
for i in range(nranks):
self.comb += [
phase.cke[i].eq(self._control.storage[1])
for phase in inti.phases
]
self.comb += [
phase.odt[i].eq(self._control.storage[2])
for phase in inti.phases if hasattr(phase, "odt")
]
self.comb += [
phase.reset_n.eq(self._control.storage[3]) for phase in inti.phases
if hasattr(phase, "reset_n")
]
def __init__(self):
self.mem = Memory(128, 8)
self.read_port = self.mem.get_port()
self.specials += self.mem, self.read_port
self.dfi = dfi.Interface(addressbits=14,
bankbits=3,
nranks=1,
databits=2 * 16,
nphases=4)
self.submodules.scratchpad = Scratchpad(self.mem, self.dfi)
def __init__(self):
super().__init__()
self.dfi = dfi.Interface(addressbits=14,
bankbits=3,
nranks=1,
databits=2 * 16,
nphases=4)
self.submodules.rank_decoder = OneHotDecoder(1)
self.submodules.executor = DFIExecutor(self.dfi, self.decoder,
self.rank_decoder)
def __init__(self,
controller_settings = None,
phy_settings = None,
geom_settings = None,
timing_settings = None):
# Update settings if provided
def updated(settings, update):
copy = settings.copy()
copy.update(update or {})
return copy
controller_settings = updated(self.default_controller_settings, controller_settings)
phy_settings = updated(self.default_phy_settings, phy_settings)
geom_settings = updated(self.default_geom_settings, geom_settings)
timing_settings = updated(self.default_timing_settings, timing_settings)
# Use simpler settigns to include only Multiplexer-specific members
class SimpleSettings(Settings):
def __init__(self, **kwargs):
self.set_attributes(kwargs)
settings = SimpleSettings(**controller_settings)
settings.phy = SimpleSettings(**phy_settings)
settings.geom = SimpleSettings(**geom_settings)
settings.timing = SimpleSettings(**timing_settings)
settings.geom.addressbits = max(settings.geom.rowbits, settings.geom.colbits)
self.settings = settings
# Create interfaces and stubs required to instantiate Multiplexer
abits = settings.geom.addressbits
babits = settings.geom.bankbits
nbanks = 2**babits
nranks = settings.phy.nranks
self.bank_machines = [BankMachineStub(abits=abits, babits=babits)
for _ in range(nbanks*nranks)]
self.refresher = RefresherStub(abits=abits, babits=babits)
self.dfi = dfi.Interface(
addressbits = abits,
bankbits = babits,
nranks = settings.phy.nranks,
databits = settings.phy.dfi_databits,
nphases = settings.phy.nphases)
address_align = log2_int(burst_lengths[settings.phy.memtype])
self.interface = LiteDRAMInterface(address_align=address_align, settings=settings)
# Add Multiplexer
self.submodules.multiplexer = Multiplexer(settings, self.bank_machines, self.refresher,
self.dfi, self.interface)
# Add helpers for driving bank machines/refresher
self.bm_drivers = [CmdRequestRWDriver(bm.cmd, i) for i, bm in enumerate(self.bank_machines)]
self.refresh_driver = CmdRequestRWDriver(self.refresher.cmd, i=1)
def __init__(self, nranks, dfi_databits, nphases):
a, ba = 13, 3
nop = Record(cmd_request_layout(a=a, ba=ba))
choose_cmd = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
choose_req = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
refresher_cmd = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
self.commands = [nop, choose_cmd, choose_req, refresher_cmd]
self.dfi = dfi.Interface(addressbits=a, bankbits=ba, nranks=nranks, databits=dfi_databits,
nphases=nphases)
self.submodules.steerer = _Steerer(self.commands, self.dfi)
# NOP is not an endpoint and does not have is_* signals
self.drivers = [CmdRequestRWDriver(req, i, ep_layout=i != 0, rw_layout=i != 0)
for i, req in enumerate(self.commands)]
def __init__(self, phy_settings, geom_settings, timing_settings,
controller_settings=ControllerSettings()):
self.settings = settings = controller_settings
self.settings.phy = phy_settings
self.settings.geom = geom_settings
self.settings.timing = timing_settings
burst_lengths = {
"SDR": 1,
"DDR": 4,
"LPDDR": 4,
"DDR2": 4,
"DDR3": 8
}
address_align = log2_int(burst_lengths[phy_settings.memtype])
self.dfi = dfi.Interface(geom_settings.addressbits,
geom_settings.bankbits,
phy_settings.dfi_databits,
phy_settings.nphases)
self.nrowbits = settings.geom.colbits - address_align
self.interface = common.LiteDRAMInterface(address_align, settings)
# # #
self.submodules.refresher = Refresher(self.settings)
bank_machines = []
for i in range(2**geom_settings.bankbits):
bank_machine = BankMachine(i,
self.interface.aw,
address_align,
settings)
bank_machines.append(bank_machine)
self.submodules += bank_machine
self.comb += getattr(self.interface, "bank"+str(i)).connect(bank_machine.req)
# FIXME: simulation workaround
if phy_settings.memtype == "DDR3" and phy_settings.nphases == 2:
self.comb += bank_machine.req.adr[-1].eq(0)
self.submodules.multiplexer = Multiplexer(settings,
bank_machines,
self.refresher,
self.dfi,
self.interface)
def __init__(self, phy_settings, geom_settings, timing_settings,
controller_settings=ControllerSettings()):
self.settings = settings = controller_settings
self.settings.phy = phy_settings
self.settings.geom = geom_settings
self.settings.timing = timing_settings
if settings.phy.memtype in ["SDR"]:
burst_length = phy_settings.nphases*1 # command multiplication*SDR
elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
burst_length = phy_settings.nphases*2 # command multiplication*DDR
address_align = log2_int(burst_length)
self.dfi = dfi.Interface(geom_settings.addressbits,
geom_settings.bankbits,
phy_settings.dfi_databits,
phy_settings.nphases)
self.nrowbits = settings.geom.colbits - address_align
self.interface = common.LiteDRAMInterface(address_align, settings)
# # #
self.submodules.refresher = Refresher(self.settings)
bank_machines = []
for i in range(2**geom_settings.bankbits):
bank_machine = BankMachine(i,
self.interface.aw,
address_align,
settings)
bank_machines.append(bank_machine)
self.submodules += bank_machine
self.comb += getattr(self.interface, "bank"+str(i)).connect(bank_machine.req)
self.submodules.multiplexer = Multiplexer(settings,
bank_machines,
self.refresher,
self.dfi,
self.interface)
def __init__(self,
phy_settings,
geom_settings,
timing_settings,
controller_settings=ControllerSettings()):
address_align = log2_int(burst_lengths[phy_settings.memtype])
self.settings = settings = controller_settings
self.settings.phy = phy_settings
self.settings.geom = geom_settings
self.settings.timing = timing_settings
self.dfi = dfi.Interface(geom_settings.addressbits,
geom_settings.bankbits, phy_settings.nranks,
phy_settings.dfi_databits,
phy_settings.nphases)
self.interface = interface = LiteDRAMInterface(address_align, settings)
# # #
# refresher
refresher = Refresher(settings)
self.submodules += refresher
# bank machines
bank_machines = []
for i in range(phy_settings.nranks * (2**geom_settings.bankbits)):
bank_machine = BankMachine(i, interface.address_width,
address_align, phy_settings.nranks,
settings)
bank_machines.append(bank_machine)
self.submodules += bank_machine
self.comb += getattr(interface,
"bank" + str(i)).connect(bank_machine.req)
# multiplexer
self.submodules.multiplexer = Multiplexer(settings, bank_machines,
refresher, self.dfi,
interface)
def __init__(self, payload):
self.mem_scratchpad = Memory(128, 8)
self.mem_payload = Memory(32, 32, init=payload)
self.specials += self.mem_scratchpad, self.mem_payload
self.dfi = dfi.Interface(addressbits=14,
bankbits=3,
nranks=1,
databits=2 * 16,
nphases=4)
self.dfi_sel = Signal()
self.submodules.payload_executor = PayloadExecutor(
self.mem_payload,
self.mem_scratchpad,
self.dfi,
self.dfi_sel,
nranks=1,
bankbits=3,
rowbits=14,
colbits=10,
rdphase=2)
self.dfi_history: list[HistoryEntry] = []
