def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False, **kwargs):
platform = mist.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on MIST",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = MT48LC16M16(sys_clk_freq, "1:1"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs):
platform = max1000.Platform()
kwargs["integrated_rom_size"] = 0x6000
kwargs["integrated_sram_size"] = 0x1000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on CYC1000",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L64322A(sys_clk_freq, "1:1"), # Winbond W9864G6JT
l2_cache_size = kwargs.get("l2_size", 0)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self,
toolchain="trellis",
sys_clk_freq=int(48e6),
sdram_module_cls="AS4C32M8",
**kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Hackaday Badge",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M8(sys_clk_freq, "1:1"),
l2_cache_size=kwargs.get("l2_size", 8192))
def __init__(self, platform):
sys_clk_freq = int(75e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x6000)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDRAM ------------------------------------------------------------------------------------
# phy
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
# module
sdram_module = M12L64322A(sys_clk_freq, "1:1")
# controller
self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
# bist
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.add_csr("sdram_checker")
# Led --------------------------------------------------------------------------------------
counter = Signal(32)
self.sync += counter.eq(counter + 1)
self.comb += platform.request("user_led").eq(counter[26])
def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, **kwargs):
platform = c10lprefkit.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=MT48LC16M16(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self,
device="LFE5U-45F",
toolchain="diamond",
sys_clk_freq=int(50e6),
sdram_module_cls="MT48LC16M16",
**kwargs):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
sdram_module = getattr(litedram_modules,
sdram_module_cls)(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
platform = de2_115.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE2-115",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16320(self.clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
def __init__(self, **kwargs):
platform = linsn_rv901t.Platform()
sys_clk_freq = int(75e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Linsn RV901T",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L64322A(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(80e6), **kwargs):
platform = minispartan6.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C16M16(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = cyc1000.Platform()
SoCSDRAM.__init__(
self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
# integrated_main_ram_size=0x4000,
**kwargs)
self.submodules.crg = _CRG(platform)
# self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7)))
# self.add_csr("leds", allow_user_defined=True)
# self.submodules.leds = ClassicLed(platform.request("user_led", 0))
self.add_csr("gpio_leds", allow_user_defined=True)
self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
# use micron device as winbond and ISSI not available
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
toolchain="trellis",
sys_clk_freq=int(48e6),
sdram_module_cls="AS4C32M8",
**kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Hackaday Badge",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M8(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs):
platform = de1soc.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE1-SoC",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16320(sys_clk_freq, "1:1"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = c10lprefkit.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]),
self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC16M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self,
device="LFE5U-45F",
toolchain="trellis",
sys_clk_freq=int(50e6),
sdram_module_cls="MT48LC16M16",
**kwargs):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=getattr(litedram_modules,
sdram_module_cls)(sys_clk_freq,
"1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_led_chaser=True, **kwargs):
platform = linsn_rv901t.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Linsn RV901T",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L64322A(sys_clk_freq, "1:1"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy))
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, device, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = max1000.Platform(device)
# SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
# integrated_rom_size=0x8000,
# **kwargs)
# csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
SoCSDRAM.__init__(
self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x6000,
# integrated_main_ram_size=0x4000,
**kwargs)
self.mem_map['spiflash'] = 0x20000000
spiflash_pads = platform.request('spiflash')
self.add_memory_region("spiflash", self.mem_map["spiflash"],
8 * 1024 * 1024)
self.submodules.spiflash = SpiFlash(spiflash_pads,
dummy=8,
div=4,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
#self.spiflash.add_clk_primitive("xc7");
# 8 MB flash: W74M64FVSSIQ
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map['spiflash'])
# spi_flash.py supports max 16MB linear space
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.submodules.crg = _CRG(platform)
# self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7)))
self.add_csr("leds", allow_user_defined=True)
self.submodules.leds = ClassicLed(platform.request("user_led", 0))
# self.add_csr("gpio_leds", allow_user_defined=True)
self.add_csr("gpio_leds", allow_user_defined=True)
self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
# use micron device as winbond and ISSI not available
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, device, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = max1000.Platform(device)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x6000,
**kwargs)
self.mem_map['spiflash'] = 0x20000000
spiflash_pads = platform.request('spiflash')
self.add_memory_region("spiflash", self.mem_map["spiflash"],
8 * 1024 * 1024)
self.submodules.spiflash = SpiFlash(spiflash_pads,
dummy=8,
div=4,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
# 8 MB flash: W74M64FVSSIQ
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map['spiflash'])
# spi_flash.py supports max 16MB linear space
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.submodules.crg = _CRG(platform)
# self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7)))
self.add_csr("leds", allow_user_defined=True)
self.submodules.leds = ClassicLed(platform.request("user_led", 0))
#
# self.add_csr("gpio_leds", allow_user_defined=True)
# self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
# use micron device as winbond and ISSI not available
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# include all unused pins as generic BBIO basic IP core
bbio_pads = platform.request("bbio")
# we can exclue any number of I/O pins to be included
self.submodules.bbio = bbioBasic(bbio_pads, exclude=None)
self.add_wb_slave(mem_decoder(self.mem_map["bbio"]), self.bbio.bus)
self.add_memory_region("bbio", self.mem_map["bbio"], 4 * 4 * 1024)
def __init__(self,
board,
revision,
with_ethernet=False,
with_etherbone=False,
sys_clk_freq=60e6,
**kwargs):
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Colorlight " + board.upper(),
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in [
"serial", "bridge"
] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll=with_usb_pll,
with_rst=with_rst)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
def __init__(self,
sys_clk_freq=int(50e6),
with_mister_sdram=False,
with_mister_vga=False,
**kwargs):
platform = de10nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE10-Nano",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_sdram=with_mister_sdram)
# SDR SDRAM --------------------------------------------------------------------------------
if with_mister_sdram and not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M16(self.clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# VGA terminal -----------------------------------------------------------------------------
if with_mister_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal",
self.terminal.bus,
region=SoCRegion(origin=0x30000000,
size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync.eq(terminal.vsync),
vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[2:8]),
vga_pads.green.eq(terminal.green[2:8]),
vga_pads.blue.eq(terminal.blue[2:8])
]
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(75e6),
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
with_led_chaser=True,
**kwargs):
platform = linsn_rv901t.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Linsn RV901T",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L64322A(sys_clk_freq, "1:1"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy),
tx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy,
with_timing_constraints=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy,
with_timing_constraints=False)
# Timing Constraints.
platform.add_period_constraint(
platform.lookup_request("eth_clocks", eth_phy).rx, 1e9 / 125e6)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
platform.lookup_request("eth_clocks", eth_phy).rx)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
revision,
with_ethernet=False,
with_etherbone=False,
sys_clk_freq=60e6,
**kwargs):
platform = colorlight_5a_75b.Platform(revision=revision)
if (with_etherbone):
sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in [
"serial", "bridge"
] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll=with_usb_pll,
with_rst=with_rst)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
def __init__(self, **kwargs):
platform = linsn_rv901t.Platform()
sys_clk_freq = int(75e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = M12L64322A(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
def __init__(self, platform, **kwargs):
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de10lite.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16320(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, **kwargs):
platform = de0nano.Platform()
SoCSDRAM.__init__(self,
platform,
clk_freq=100 * 1000000,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), )
sdram_module = IS42S16160(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
sys_clk_freq=int(50e6),
with_led_chaser=True,
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = c10lprefkit.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on C10 LP RefKit",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=MT48LC16M16(sys_clk_freq, "1:1"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
sdram_module = AS4C32M8(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, device="LFE5U-85F", toolchain="diamond", **kwargs):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, **kwargs):
platform = versa_ecp5.Platform(toolchain="trellis")
platform.add_extension(versa_ecp5._ecp5_soc_hat_io)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C32M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de1soc.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
# ISSI IS42S16320D-7TL
sdram_module = IS42S16320(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
