def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_led_chaser=True,
with_jtagbone=True,
with_spi_flash=False,
with_pmod_gpio=False,
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_dram=not self.integrated_main_ram_size)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=S25FL128L(Codes.READ_1_1_4),
rate="1:2",
with_master=True)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(arty.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
args=None,
ip_address="192.168.100.50",
mac_address=0x10e2d5000001,
udp_port=1234,
**kwargs):
if not args.sim:
platform = arty.Platform(toolchain=toolchain)
else:
platform = SimPlatform("SIM", _io)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
if not args.sim:
self.submodules.crg = _CRG(platform, sys_clk_freq, args)
else:
self.submodules.crg = CRG(platform.request("sys_clk"))
# DDR3 SDRAM -------------------------------------------------------------------------------
if not args.sim:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
else:
from litedram.gen import get_dram_ios
core_config = dict()
core_config["sdram_module_nb"] = 2 # Number of byte groups
core_config["sdram_rank_nb"] = 1 # Number of ranks
core_config['sdram_module'] = getattr(litedram_modules,
'MT41K128M16')
core_config["memtype"] = "DDR3" # DRAM type
platform.add_extension(get_dram_ios(core_config))
sdram_module = core_config["sdram_module"](
sys_clk_freq,
rate={
"DDR2": "1:2",
"DDR3": "1:4",
"DDR4": "1:4"
}[core_config["memtype"]])
from litex.tools.litex_sim import get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
phy_settings = get_sdram_phy_settings(
memtype=sdram_module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sdram_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(
module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=3,
)
class ControllerDynamicSettings(Module, AutoCSR, AutoDoc):
"""Allows to change LiteDRAMController behaviour at runtime"""
def __init__(self):
self.refresh = CSRStorage(
reset=1,
description="Enable/disable Refresh commands sending")
self.submodules.controller_settings = ControllerDynamicSettings()
self.add_csr("controller_settings")
controller_settings = ControllerSettings()
controller_settings.with_auto_precharge = True
controller_settings.with_refresh = self.controller_settings.refresh.storage
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=0,
l2_cache_min_data_width=0, #128
l2_cache_reverse=True,
controller_settings=controller_settings)
# Ethernet / Etherbone ---------------------------------------------------------------------
if not args.sim:
# Ethernet PHY (arty)
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
udp_port=udp_port)
else:
# Ethernet PHY (simulation)
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
udp_port,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
if args.sim:
self.comb += platform.trace.eq(1)
# Rowhammer --------------------------------------------------------------------------------
self.submodules.rowhammer_dma = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma)
self.add_csr("rowhammer")
def add_xram(self, name, origin, mem, mode='rw'):
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion
ram = wishbone.SRAM(mem,
bus=wishbone.Interface(data_width=mem.width),
read_only='w' not in mode)
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
self.submodules += wishbone.Converter(ram_bus, ram.bus)
region = SoCRegion(origin=origin,
size=mem.width // 8 * mem.depth,
mode=mode)
self.bus.add_slave(name, ram_bus, region)
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name), colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
# Bist -------------------------------------------------------------------------------------
if not args.no_memory_bist:
# ------------------------------ writer ------------------------------------
dram_wr_port = self.sdram.crossbar.get_port()
self.submodules.writer = Writer(dram_wr_port)
self.add_csr('writer')
# TODO: Rename as 'pattern_wr_w?'
add_xram(self,
name='pattern_w0',
mem=self.writer.memory_w0,
origin=0x20000000)
add_xram(self,
name='pattern_w1',
mem=self.writer.memory_w1,
origin=0x21000000)
add_xram(self,
name='pattern_w2',
mem=self.writer.memory_w2,
origin=0x22000000)
add_xram(self,
name='pattern_w3',
mem=self.writer.memory_w3,
origin=0x23000000)
add_xram(self,
name='pattern_adr',
mem=self.writer.memory_adr,
origin=0x24000000)
# ----------------------------- reader -------------------------------------
dram_rd_port = self.sdram.crossbar.get_port()
self.submodules.reader = Reader(dram_rd_port)
self.add_csr('reader')
add_xram(self,
name='pattern_rd_w0',
mem=self.reader.memory_w0,
origin=0x30000000)
add_xram(self,
name='pattern_rd_w1',
mem=self.reader.memory_w1,
origin=0x31000000)
add_xram(self,
name='pattern_rd_w2',
mem=self.reader.memory_w2,
origin=0x32000000)
add_xram(self,
name='pattern_rd_w3',
mem=self.reader.memory_w3,
origin=0x33000000)
add_xram(self,
name='pattern_rd_adr',
mem=self.reader.memory_adr,
origin=0x34000000)
# Payload executor -------------------------------------------------------------------------
if not args.no_payload_executor:
# TODO: disconnect bus during payload execution
phy_settings = self.sdram.controller.settings.phy
scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases
scratchpad_size = 2**10
payload_mem = Memory(32, 2**10)
scratchpad_mem = Memory(scratchpad_width,
scratchpad_size // (scratchpad_width // 8))
self.specials += payload_mem, scratchpad_mem
add_xram(self, name='payload', mem=payload_mem, origin=0x35000000)
add_xram(self,
name='scratchpad',
mem=scratchpad_mem,
origin=0x36000000,
mode='r')
self.submodules.payload_executor = PayloadExecutor(
mem_payload=payload_mem,
mem_scratchpad=scratchpad_mem,
dfi=self.sdram.dfii.ext_dfi,
dfi_sel=self.sdram.dfii.ext_dfi_sel,
nranks=self.sdram.controller.settings.phy.nranks,
bankbits=self.sdram.controller.settings.geom.bankbits,
rowbits=self.sdram.controller.settings.geom.rowbits,
colbits=self.sdram.controller.settings.geom.colbits,
rdphase=self.sdram.controller.settings.phy.rdphase,
)
self.payload_executor.add_csrs()
self.add_csr('payload_executor')
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
with_jtagbone=True, with_spi_flash=False, **kwargs):
platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
if (kwargs["uart_name"] == "serial") and (not with_daughterboard):
kwargs["uart_name"] = "gpio_serial"
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QMTech XC7A35T" + (" + Daughterboard" if with_daughterboard else ""),
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import MT25QL128
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=MT25QL128(Codes.READ_1_1_1), with_master=True)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
if not with_daughterboard and kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_serial"
def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, **kwargs):
platform = sds1104xe.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Siglent SDS1104X-E",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_etherbone)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# FIXME: Simplify LiteEth Hybrid MAC integration.
from liteeth.common import convert_ip
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
from liteeth.core.udp import LiteEthUDP
from liteeth.core.icmp import LiteEthICMP
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8,
interface = "hybrid",
endianness = self.cpu.endianness,
hw_mac = etherbone_mac_address)
# Software Interface.
self.add_memory_region("ethmac", getattr(self.mem_map, "ethmac", None), 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Hardware Interface.
self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8)
self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8)
self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8)
self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface.
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk
eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/self.ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/self.ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Video ------------------------------------------------------------------------------------
video_timings = ("800x480@60Hz", {
"pix_clk" : 33.3e6,
"h_active" : 800,
"h_blanking" : 256,
"h_sync_offset" : 210,
"h_sync_width" : 1,
"v_active" : 480,
"v_blanking" : 45,
"v_sync_offset" : 22,
"v_sync_width" : 1,
})
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("lcd"), clock_domain="dvi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings=video_timings, clock_domain="dvi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings=video_timings, clock_domain="dvi")
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
ident_version=True,
with_jtagbone=True,
with_mapped_flash=False,
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
kwargs["cpu_type"] = "vexriscv_smp"
kwargs["cpu_variant"] = "linux"
kwargs["cpu_cls"] = VexRiscvSMP
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_mapped_flash)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Flash (through LiteSPI, experimental).
if with_mapped_flash:
self.submodules.spiflash_phy = LiteSPIPHY(
platform.request("spiflash4x"), S25FL128L(Codes.READ_1_1_4))
self.submodules.spiflash_mmap = LiteSPI(
self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=S25FL128L.total_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# USB Host ---------------------------------------------------------------------------------
from litex.soc.cores.usb_ohci import USBOHCI
from litex.build.generic_platform import Subsignal, Pins, IOStandard
_usb_pmod_ios = [(
"usb_pmoda",
0,
Subsignal("dp", Pins("pmoda:0")),
Subsignal("dm", Pins("pmoda:4")),
IOStandard("LVCMOS33"),
)]
platform.add_extension(_usb_pmod_ios)
self.submodules.usb_ohci = USBOHCI(platform,
platform.request("usb_pmoda"),
usb_clk_freq=int(48e6))
self.bus.add_slave("usb_ohci_ctrl",
self.usb_ohci.wb_ctrl,
region=SoCRegion(origin=self.mem_map["usb_ohci"],
size=0x100000,
cached=False)) # FIXME: Mapping.
self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
def __init__(self,
variant="ep4ce15",
sys_clk_freq=int(50e6),
with_daughterboard=False,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_led_chaser=True,
with_video_terminal=False,
with_video_framebuffer=False,
sdram_rate="1:1",
**kwargs):
platform = qmtech_ep4cex5.Platform(
variant=variant, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on QMTECH EP4CE15" +
(" + Daughterboard" if with_daughterboard else ""),
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_ethernet=with_ethernet
or with_etherbone,
with_vga=with_video_terminal
or with_video_framebuffer,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"),
clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(100e6),
with_etherbone=True,
eth_ip="192.168.1.50",
**kwargs):
platform = sds1104xe.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Siglent SDS1104X-E",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# FIXME: Simplify LiteEth Hybrid MAC integration.
from liteeth.common import convert_ip
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
from liteeth.core.udp import LiteEthUDP
from liteeth.core.icmp import LiteEthICMP
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY
ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.submodules += ethphy
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=ethphy,
dw=8,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# Software Interface.
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Hardware Interface.
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=8)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=8)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=8)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=8)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = ethphy.crg.cd_eth_rx.clk
eth_tx_clk = ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk,
1e9 / ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk,
1e9 / ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
eth_rx_clk, eth_tx_clk)
def __init__(self,
sys_clk_freq=int(100e6),
cpu_count=1,
with_ethernet=False,
with_analyzer=False,
**kwargs):
VexRiscvSMP.litedram_width = 128
VexRiscvSMP.ibus_width = 64
VexRiscvSMP.dbus_width = 64
VexRiscvSMP.coherent_dma = True
platform = arty.Platform()
platform.add_extension(arty._sdcard_pmod_io) # MicroSD PMOD on JD.
platform.add_extension(arty._usb_uart_pmod_io) # USB UART PMOD on JA.
# SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_size"] = 0x10000
kwargs["csr_data_width"] = 8
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_cls=VexRiscvSMP,
cpu_variant="default",
**kwargs)
self.add_constant("config_cpu_count", cpu_count) # for dts generation
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0C00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True,
controller_settings=ControllerSettings(
cmd_buffer_buffered=False,
with_auto_precharge=False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# JTAG ---------------------------------------------------------------------------------
self.submodules.jtag = S7JTAG()
self.comb += self.cpu.jtag_clk.eq(self.jtag.tck)
self.comb += self.cpu.jtag_enable.eq(1)
self.comb += self.cpu.jtag_capture.eq(self.jtag.capture)
self.comb += self.cpu.jtag_shift.eq(self.jtag.shift)
self.comb += self.cpu.jtag_update.eq(self.jtag.update)
self.comb += self.cpu.jtag_reset.eq(self.jtag.reset)
self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi)
self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
self.add_uartbone("usb_uart")
analyzer_signals = [self.cpu.dma_buses[0]]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
args=None,
ip_address="192.168.100.50",
mac_address=0x10e2d5000001,
udp_port=1234,
**kwargs):
if not args.sim:
platform = arty.Platform(toolchain=toolchain)
else:
platform = Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
if not args.sim:
self.submodules.crg = _CRG(platform, sys_clk_freq, args)
else:
self.submodules.crg = CRG(platform.request("sys_clk"))
# DDR3 SDRAM -------------------------------------------------------------------------------
if not args.sim:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
else:
from litedram.gen import get_dram_ios
core_config = dict()
core_config["sdram_module_nb"] = 2 # Number of byte groups
core_config["sdram_rank_nb"] = 1 # Number of ranks
core_config['sdram_module'] = getattr(litedram_modules,
'MT41K128M16')
core_config["memtype"] = "DDR3" # DRAM type
platform.add_extension(get_dram_ios(core_config))
sdram_module = core_config["sdram_module"](
sys_clk_freq,
rate={
"DDR2": "1:2",
"DDR3": "1:4",
"DDR4": "1:4"
}[core_config["memtype"]])
from litex.tools.litex_sim import get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
phy_settings = get_sdram_phy_settings(
memtype=sdram_module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sdram_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(
module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=3,
)
class ControllerDynamicSettings(Module, AutoCSR, AutoDoc):
"""Allows to change LiteDRAMController behaviour at runtime"""
def __init__(self):
self.refresh = CSRStorage(
reset=1,
description="Enable/disable Refresh commands sending")
self.submodules.controller_settings = ControllerDynamicSettings()
self.add_csr("controller_settings")
controller_settings = ControllerSettings()
controller_settings.with_auto_precharge = True
controller_settings.with_refresh = self.controller_settings.refresh.storage
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=0,
l2_cache_min_data_width=0, #128
l2_cache_reverse=True,
controller_settings=controller_settings)
# Ethernet / Etherbone ---------------------------------------------------------------------
if not args.sim:
# Ethernet PHY (arty)
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
udp_port=udp_port)
else:
# Ethernet PHY (simulation)
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
udp_port,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# Analyzer ---------------------------------------------------------------------------------
# analyzer_signals = [
# self.bus.masters['master0'].stb,
# self.bus.masters['master0'].cyc,
# self.bus.masters['master0'].adr,
# self.bus.masters['master0'].we,
# self.bus.masters['master0'].ack,
# self.bus.masters['master0'].sel,
# self.bus.masters['master0'].dat_w,
# self.bus.masters['master0'].dat_r,
# ]
# from litescope import LiteScopeAnalyzer
# self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
# depth = 512,
# clock_domain = "sys",
# csr_csv = "analyzer.csv")
# self.add_csr("analyzer")
if args.sim:
self.comb += platform.trace.eq(1)
# Rowhammer --------------------------------------------------------------------------------
from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter
self.submodules.rowhammer_dma = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma)
self.add_csr("rowhammer")
# Bist -------------------------------------------------------------------------------------
if not args.no_memory_bist:
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
def add_xram(self, name, origin, mem):
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
ram = wishbone.SRAM(mem, bus=ram_bus)
self.bus.add_slave(
name, ram.bus,
SoCRegion(origin=origin,
size=mem.width * mem.depth,
mode='rw'))
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name), colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
return
# ------------------------------ writer ------------------------------------
memory_w0 = Memory(32, 1024)
memory_w1 = Memory(32, 1024)
memory_w2 = Memory(32, 1024)
memory_w3 = Memory(32, 1024)
memory_adr = Memory(32, 1024)
add_xram(self, name='pattern_w0', mem=memory_w0, origin=0x20000000)
add_xram(self, name='pattern_w1', mem=memory_w1, origin=0x21000000)
add_xram(self, name='pattern_w2', mem=memory_w2, origin=0x22000000)
add_xram(self, name='pattern_w3', mem=memory_w3, origin=0x23000000)
add_xram(self,
name='pattern_adr',
mem=memory_adr,
origin=0x24000000)
class Writer(Module, AutoCSR):
def __init__(self, dram_port, w0_port, w1_port, w2_port,
w3_port, adr_port):
self.reset = CSRStorage()
self.start = CSRStorage()
self.done = CSRStatus()
self.count = CSRStorage(size=(32 * 1))
self.mem_base = CSRStorage(size=32)
self.mem_mask = CSRStorage(size=32)
self.data_mask = CSRStorage(size=32) # patterns
dma = LiteDRAMDMAWriter(dram_port, fifo_depth=1)
self.submodules += dma
cmd_counter = Signal(32)
self.comb += [
w0_port.adr.eq(cmd_counter & self.data_mask.storage),
w1_port.adr.eq(cmd_counter & self.data_mask.storage),
w2_port.adr.eq(cmd_counter & self.data_mask.storage),
w3_port.adr.eq(cmd_counter & self.data_mask.storage),
adr_port.adr.eq(cmd_counter & self.data_mask.storage),
]
self.comb += [
dma.sink.address.eq(self.mem_base.storage +
adr_port.dat_r +
(cmd_counter
& self.mem_mask.storage)),
dma.sink.data.eq(
Cat(w0_port.dat_r, w1_port.dat_r, w2_port.dat_r,
w3_port.dat_r)),
]
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act(
"IDLE",
If(
self.start.storage,
NextValue(cmd_counter, 0),
NextState("WAIT"),
))
fsm.act(
"WAIT",
If(cmd_counter >= self.count.storage,
NextState("DONE")).Else(NextState("RUN")))
fsm.act(
"RUN", dma.sink.valid.eq(1),
If(dma.sink.ready,
NextValue(cmd_counter, cmd_counter + 1),
NextState("WAIT")))
fsm.act("DONE", self.done.status.eq(1),
If(self.reset.storage, NextState("IDLE")))
dram_port = self.sdram.crossbar.get_port()
w0_port = memory_w0.get_port()
w1_port = memory_w1.get_port()
w2_port = memory_w2.get_port()
w3_port = memory_w3.get_port()
adr_port = memory_adr.get_port()
self.specials += w0_port, w1_port, w2_port, w3_port, adr_port
self.submodules.writer = Writer(dram_port, w0_port, w1_port,
w2_port, w3_port, adr_port)
self.add_csr('writer')
# ----------------------------- reader -------------------------------------
memory_rd_w0 = Memory(32, 1024)
memory_rd_w1 = Memory(32, 1024)
memory_rd_w2 = Memory(32, 1024)
memory_rd_w3 = Memory(32, 1024)
memory_rd_adr = Memory(32, 1024)
add_xram(self,
name='pattern_rd_w0',
mem=memory_rd_w0,
origin=0x30000000)
add_xram(self,
name='pattern_rd_w1',
mem=memory_rd_w1,
origin=0x31000000)
add_xram(self,
name='pattern_rd_w2',
mem=memory_rd_w2,
origin=0x32000000)
add_xram(self,
name='pattern_rd_w3',
mem=memory_rd_w3,
origin=0x33000000)
add_xram(self,
name='pattern_rd_adr',
mem=memory_rd_adr,
origin=0x34000000)
class Reader(Module, AutoCSR):
def __init__(self, dram_port, w0_port, w1_port, w2_port,
w3_port, adr_port):
self.reset = CSRStorage()
self.start = CSRStorage()
self.done = CSRStatus()
self.count = CSRStorage(size=32)
self.pointer = CSRStatus(size=32)
self.mem_base = CSRStorage(size=32)
self.mem_mask = CSRStorage(size=32)
self.data_mask = CSRStorage(size=32) # patterns
dma = LiteDRAMDMAReader(dram_port,
fifo_depth=1,
fifo_buffered=False)
self.submodules += dma
cmd_counter = Signal(32)
self.comb += [
w0_port.adr.eq(cmd_counter & self.data_mask.storage),
w1_port.adr.eq(cmd_counter & self.data_mask.storage),
w2_port.adr.eq(cmd_counter & self.data_mask.storage),
w3_port.adr.eq(cmd_counter & self.data_mask.storage),
adr_port.adr.eq(cmd_counter & self.data_mask.storage),
]
data_pattern = Signal(32 * 4)
self.comb += [
dma.sink.address.eq(self.mem_base.storage +
adr_port.dat_r +
(cmd_counter
& self.mem_mask.storage)),
data_pattern.eq(
Cat(w0_port.dat_r, w1_port.dat_r, w2_port.dat_r,
w3_port.dat_r)),
]
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act(
"IDLE",
If(
self.start.storage,
NextValue(cmd_counter, 0),
NextValue(self.pointer.status, 0xdeadbeef),
NextState("WAIT"),
))
fsm.act(
"WAIT",
If(cmd_counter >= self.count.storage,
NextState("DONE")).Else(NextState("WR_ADR")))
fsm.act("WR_ADR", dma.sink.valid.eq(1),
If(dma.sink.ready, NextState("RD_DATA")))
fsm.act(
"RD_DATA", dma.source.ready.eq(1),
If(
dma.source.valid,
NextValue(cmd_counter, cmd_counter + 1),
If(dma.source.data != data_pattern,
NextValue(self.pointer.status, cmd_counter)),
NextState("WAIT")))
fsm.act("DONE", self.done.status.eq(1),
If(self.reset.storage, NextState("IDLE")))
dram_rd_port = self.sdram.crossbar.get_port()
w0_port = memory_rd_w0.get_port()
w1_port = memory_rd_w1.get_port()
w2_port = memory_rd_w2.get_port()
w3_port = memory_rd_w3.get_port()
adr_port = memory_rd_adr.get_port()
self.specials += w0_port, w1_port, w2_port, w3_port, adr_port
self.submodules.reader = Reader(dram_rd_port, w0_port, w1_port,
w2_port, w3_port, adr_port)
self.add_csr('reader')
def __init__(self,
sys_clk_freq=int(80e6),
toolchain="trellis",
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = fpc_iii.Platform(toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] == "serial":
# Defaults to USB FIFO since no real serial.
kwargs["uart_name"] = "usb_fifo"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on FPC-III",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
ddram = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(
ddram, sys_clk_freq, clk_polarity=1) # clk_p/n swapped.
self.ddrphy.settings.rtt_nom = "disabled"
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits))
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=IS43TR16256A(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x20000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
self.comb += platform.request("dram_vtt_en").eq(
0 if self.integrated_main_ram_size else 1)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6)):
platform = arty.Platform()
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteEth bench on Arty",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
with_hw_init_reset=False)
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# SRAM -------------------------------------------------------------------------------------
self.add_ram("sram", 0x20000000, 0x1000)
# UDP Streamer -----------------------------------------------------------------------------
from liteeth.frontend.stream import LiteEthUDPStreamer
self.submodules.udp_streamer = udp_streamer = LiteEthUDPStreamer(
udp=self.ethcore.udp,
ip_address="192.168.1.100",
udp_port=6000,
)
# Leds -------------------------------------------------------------------------------------
leds_pads = platform.request_all("user_led")
# Led Chaser (Default).
chaser_leds = Signal(len(leds_pads))
self.submodules.leds = LedChaser(pads=chaser_leds,
sys_clk_freq=sys_clk_freq)
# Led Control from UDP Streamer RX.
udp_leds = Signal(len(leds_pads))
self.comb += udp_streamer.source.ready.eq(1)
self.sync += If(udp_streamer.rx.source.valid,
udp_leds.eq(udp_streamer.source.data))
# Led Mux: Switch to received UDP value for 1s then switch back to Led Chaser.
self.submodules.leds_timer = leds_timer = WaitTimer(sys_clk_freq)
self.comb += [
leds_timer.wait.eq(~udp_streamer.rx.source.valid
), # Reload Timer on new UDP value.
If(leds_timer.done,
leds_pads.eq(chaser_leds)).Else(leds_pads.eq(udp_leds))
]
# Switches ---------------------------------------------------------------------------------
if False:
# Resynchronize Swiches inputs.
switches_pads = platform.request_all("user_sw")
switches = Signal(len(switches_pads))
self.specials += MultiReg(switches_pads, switches)
# Send Switches value on UDP Streamer TX every 500ms.
switches_timer = WaitTimer(int(500e-3 * sys_clk_freq))
switches_fsm = FSM(reset_state="IDLE")
self.submodules += switches_timer, switches_fsm
switches_fsm.act("IDLE", switches_timer.wait.eq(1),
If(switches_timer.done, NextState("SEND")))
switches_fsm.act("SEND", udp_streamer.sink.valid.eq(1),
udp_streamer.sink.data.eq(switches),
If(udp_streamer.sink.ready, NextState("IDLE")))
def __init__(self,
variant="minimal",
with_sampler=False,
with_analyzer=False,
host_ip="192.168.1.100",
host_udp_port=2000):
platform = arty.Platform()
# BenchSoC ---------------------------------------------------------------------------------
bench_kwargs = {
"minimal": dict(cpu_variant="minimal",
integrated_main_ram_size=0x1000),
"standard": dict(),
}[variant]
BaseSoC.__init__(self,
sys_clk_freq=int(100e6),
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
**bench_kwargs)
# SDCard on PMODD with Digilent's Pmod MicroSD ---------------------------------------------
self.platform.add_extension(arty._sdcard_pmod_io)
self.add_sdcard("sdcard")
if with_sampler or with_analyzer:
# Etherbone ----------------------------------------------------------------------------
from liteeth.phy.mii import LiteEthPHYMII
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
if with_sampler:
# PMODB Sampler (connected to PmodTPH2 with Pmode Cable Kit) ---------------------------
_la_pmod_ios = [("la_pmod", 0,
Pins("pmoda:0 pmoda:1 pmoda:2 pmoda:3",
"pmoda:4 pmoda:5 pmoda:6 pmoda:7"),
IOStandard("LVCMOS33"))]
self.platform.add_extension(_la_pmod_ios)
self.submodules.sampler = Sampler(self.platform.request("la_pmod"))
self.add_csr("sampler")
# DRAMFIFO -----------------------------------------------------------------------------
from litedram.frontend.fifo import LiteDRAMFIFO
self.submodules.fifo = LiteDRAMFIFO(
data_width=8,
base=0x00000000,
depth=0x01000000, # 16MB
write_port=self.sdram.crossbar.get_port(mode="write",
data_width=8),
read_port=self.sdram.crossbar.get_port(mode="read",
data_width=8),
)
# UDPStreamer --------------------------------------------------------------------------
from liteeth.common import convert_ip
from liteeth.frontend.stream import LiteEthStream2UDPTX
udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8)
udp_streamer = LiteEthStream2UDPTX(ip_address=convert_ip(host_ip),
udp_port=host_udp_port,
fifo_depth=1024)
udp_streamer = ClockDomainsRenamer("eth_tx")(udp_streamer)
self.submodules += udp_streamer
udp_cdc = stream.ClockDomainCrossing([("data", 8)], "sys",
"eth_tx")
self.submodules += udp_cdc
# Sampler/FIFO/UDPStreamer flow -------------------------------------------------------------
self.comb += self.sampler.source.connect(self.fifo.sink)
self.comb += self.fifo.source.connect(udp_cdc.sink)
self.comb += udp_cdc.source.connect(udp_streamer.sink)
self.comb += udp_streamer.source.connect(udp_port.sink)
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [
self.sdphy.sdpads,
self.sdphy.cmdw.sink,
self.sdphy.cmdr.sink,
self.sdphy.cmdr.source,
self.sdphy.dataw.sink,
self.sdphy.dataw.stop,
self.sdphy.dataw.crc.source,
self.sdphy.dataw.status.status,
self.sdphy.datar.sink,
self.sdphy.datar.source,
self.sdphy.clocker.ce,
self.sdphy.clocker.stop,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=2048,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
with_daughterboard=False,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_video_terminal=False,
with_video_framebuffer=False,
ident_version=True,
with_jtagbone=True,
with_mapped_flash=False,
**kwargs):
platform = qmtech_xc7a35t.Platform(
toolchain=toolchain, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on QMTech XC7A35T" +
(" + Daughterboard" if with_daughterboard else ""),
ident_version=ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(
platform, sys_clk_freq, with_ethernet or with_etherbone,
with_video_terminal or with_video_framebuffer)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J128M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
self.platform.add_platform_command(
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]"
)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Flash (through LiteSPI, experimental).
if with_mapped_flash:
self.submodules.spiflash_phy = LiteSPIPHY(
platform.request("spiflash4x"), MT25QL128(Codes.READ_1_1_1))
self.submodules.spiflash_mmap = LiteSPI(
self.spiflash_phy,
clk_freq=sys_clk_freq,
mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get(
"spiflash", None),
size=MT25QL128.total_size,
cached=False)
self.bus.add_slave(name="spiflash",
slave=self.spiflash_mmap.bus,
region=spiflash_region)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"),
clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
if not with_daughterboard and kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_serial"
